MOVM.DB	[R0-R4], 4(R1)     // ERROR "offset must be zero"
	MOVW	CPSR, FPSR         // ERROR "illegal combination"
	MOVW	FPSR, CPSR         // ERROR "illegal combination"
	MOVW	CPSR, errors(SB)   // ERROR "illegal combination"
	MOVW	errors(SB), CPSR   // ERROR "illegal combination"
	MOVW	FPSR, errors(SB)   // ERROR "illegal combination"
	MOVW	errors(SB), FPSR   // ERROR "illegal combination"
	MOVW	F0, errors(SB)     // ERROR "illegal combination"

	STP (R14, R15), 120(RSP)
	STP (R16, R17), 136(RSP)
	STP (R19, R20), 152(RSP)
	STP (R21, R22), 168(RSP)
	STP (R23, R24), 184(RSP)
	STP (R25, R26), 200(RSP)
	MOVD NZCV, R0
	MOVD R0, 216(RSP)
	MOVD FPSR, R0
	MOVD R0, 224(RSP)
	FSTPD (F0, F1), 232(RSP)
	FSTPD (F2, F3), 248(RSP)
	FSTPD (F4, F5), 264(RSP)
	FSTPD (F6, F7), 280(RSP)
	FSTPD (F8, F9), 296(RSP)
	FSTPD (F10, F11), 312(RSP)
	FSTPD (F12, F13), 328(RSP)

	}
	if REG_R0 <= r && r <= REG_R15 {
		return fmt.Sprintf("R%d", r-REG_R0)
	}
	if REG_F0 <= r && r <= REG_F15 {
		return fmt.Sprintf("F%d", r-REG_F0)
	}

	switch r {
	case REG_FPSR:
		return "FPSR"

	case REG_FPCR:
		return "FPCR"

	case REG_CPSR:
		return "CPSR"

	case REG_SPSR:
		return "SPSR"

	case REG_MB_SY:
		return "MB_SY"
	case REG_MB_ST:
		return "MB_ST"
	case REG_MB_ISH:

func fpRegAddr(dst *sigcontext, i int) *uint64 {
	/* FP-SIMD registers are saved in sigcontext.__reserved, which is orgnized in
	the following C structs:
	struct fpsimd_context {
		struct _aarch64_ctx head;
		__u32 fpsr;
		__u32 fpcr;
		__uint128_t vregs[32];
	};
	struct _aarch64_ctx {
		__u32 magic;
		__u32 size;
	};
	So the offset of the ith FP_SIMD register is 16+i*128.
	*/

	pc    uint64     // program counter
	cpsr  uint32     // current program status register
	__pad uint32
}

type neonstate64 struct {
	v    [64]uint64 // actually [32]uint128
	fpsr uint32
	fpcr uint32
}

type mcontext64 struct {
	es exceptionstate64
	ss regs64
	ns neonstate64
}

type ucontext struct {
	uc_onstack  int32
	uc_sigmask  uint32
	uc_stack    stackt

type context struct {
	contextflags uint32
	cpsr         uint32
	x            [31]uint64 // fp is x[29], lr is x[30]
	xsp          uint64
	pc           uint64
	v            [32]neon128
	fpcr         uint32
	fpsr         uint32
	bcr          [8]uint32
	bvr          [8]uint64
	wcr          [2]uint32
	wvr          [2]uint64
}

func (c *context) ip() uintptr { return uintptr(c.pc) }

}

type Sigset_t struct {
	Val [4]uint32
}

type Reg struct {
	R    [13]uint32
	Sp   uint32
	Lr   uint32
	Pc   uint32
	Cpsr uint32
}

type FpReg struct {
	Fpsr uint32
	Fpr  [8]FpExtendedPrecision
}

type FpExtendedPrecision struct {
	Exponent    uint32
	Mantissa_hi uint32
	Mantissa_lo uint32
}

type PtraceIoDesc struct {
	Op   int32

		l.add2("STP", "LDP", reg, 16)
	}
	// Add flag registers.
	l.addSpecial(
		"MOVD NZCV, R0\nMOVD R0, %d(RSP)",
		"MOVD %d(RSP), R0\nMOVD R0, NZCV",
		8)
	l.addSpecial(
		"MOVD FPSR, R0\nMOVD R0, %d(RSP)",
		"MOVD %d(RSP), R0\nMOVD R0, FPSR",
		8)
	// TODO: FPCR? I don't think we'll change it, so no need to save.
	// Add floating point registers F0-F31.
	for i := 0; i < 31; i += 2 {
		reg := fmt.Sprintf("(F%d, F%d)", i, i+1)

	MOVW	$0xff000000, CPSR    // MOVW $4278190080, CPSR    // fff42ce3
	MOVW	FPSR, R9                                          // 109af1ee
	MOVW	FPSR, g                                           // 10aaf1ee
	MOVW	R9, FPSR                                          // 109ae1ee
	MOVW	g, FPSR                                           // 10aae1ee
	MOVW	R0>>28(R1), R2                                    // 202e91e7

	{"ESR_EL1", REG_ESR_EL1, 0x185200, SR_READ | SR_WRITE},
	{"FAR_EL1", REG_FAR_EL1, 0x186000, SR_READ | SR_WRITE},
	{"FPCR", REG_FPCR, 0x1b4400, SR_READ | SR_WRITE},
	{"FPSR", REG_FPSR, 0x1b4420, SR_READ | SR_WRITE},
	{"GCR_EL1", REG_GCR_EL1, 0x1810c0, SR_READ | SR_WRITE},
	{"GMID_EL1", REG_GMID_EL1, 0x31400, SR_READ},
	{"ICC_AP0R0_EL1", REG_ICC_AP0R0_EL1, 0x18c880, SR_READ | SR_WRITE},