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Results 1 - 10 of 37 for vdivuw (0.78 sec)

  1. src/cmd/asm/internal/asm/testdata/ppc64_p10.s

    	VDIVESQ V1, V2, V3                      // 1061130b
    	VDIVESW V1, V2, V3                      // 1061138b
    	VDIVEUD V1, V2, V3                      // 106112cb
    	VDIVEUQ V1, V2, V3                      // 1061120b
    	VDIVEUW V1, V2, V3                      // 1061128b
    	VDIVSD V1, V2, V3                       // 106111cb
    	VDIVSQ V1, V2, V3                       // 1061110b
    	VDIVSW V1, V2, V3                       // 1061118b
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 23 20:52:57 UTC 2023
    - 14.3K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/ppc64/asm9_gtables.go

    	"VEXTDUBVLX",
    	"VEXTDDVRX",
    	"VEXTDDVLX",
    	"VEXPANDWM",
    	"VEXPANDQM",
    	"VEXPANDHM",
    	"VEXPANDDM",
    	"VEXPANDBM",
    	"VDIVUW",
    	"VDIVUQ",
    	"VDIVUD",
    	"VDIVSW",
    	"VDIVSQ",
    	"VDIVSD",
    	"VDIVEUW",
    	"VDIVEUQ",
    	"VDIVEUD",
    	"VDIVESW",
    	"VDIVESQ",
    	"VDIVESD",
    	"VCTZDM",
    	"VCNTMBW",
    	"VCNTMBH",
    	"VCNTMBD",
    	"VCNTMBB",
    	"VCMPUQ",
    	"VCMPSQ",
    	"VCMPGTUQCC",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 16 20:18:50 UTC 2022
    - 42.6K bytes
    - Viewed (0)
  3. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

    	VDIVESD:        "vdivesd",
    	VDIVESQ:        "vdivesq",
    	VDIVESW:        "vdivesw",
    	VDIVEUD:        "vdiveud",
    	VDIVEUQ:        "vdiveuq",
    	VDIVEUW:        "vdiveuw",
    	VDIVSD:         "vdivsd",
    	VDIVSQ:         "vdivsq",
    	VDIVSW:         "vdivsw",
    	VDIVUD:         "vdivud",
    	VDIVUQ:         "vdivuq",
    	VDIVUW:         "vdivuw",
    	VEXPANDBM:      "vexpandbm",
    	VEXPANDDM:      "vexpanddm",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 334.7K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm/anames.go

    	"FNMULSF",
    	"FNMULSD",
    	"DIVF",
    	"DIVD",
    	"SQRTF",
    	"SQRTD",
    	"ABSF",
    	"ABSD",
    	"NEGF",
    	"NEGD",
    	"SRL",
    	"SRA",
    	"SLL",
    	"MULU",
    	"DIVU",
    	"MUL",
    	"MMUL",
    	"DIV",
    	"MOD",
    	"MODU",
    	"DIVHW",
    	"DIVUHW",
    	"MOVB",
    	"MOVBS",
    	"MOVBU",
    	"MOVH",
    	"MOVHS",
    	"MOVHU",
    	"MOVW",
    	"MOVM",
    	"SWPBU",
    	"SWPW",
    	"RFE",
    	"SWI",
    	"MULA",
    	"MULS",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 16 15:58:33 UTC 2019
    - 1.4K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/avx512enc/avx512f.s

    	VDIVPD Z16, Z21, K3, Z14                           // 6231d5435ef0
    	VDIVPD Z9, Z21, K3, Z14                            // 6251d5435ef1
    	VDIVPD Z16, Z8, K3, Z14                            // 6231bd4b5ef0
    	VDIVPD Z9, Z8, K3, Z14                             // 6251bd4b5ef1
    	VDIVPD Z16, Z21, K3, Z15                           // 6231d5435ef8
    	VDIVPD Z9, Z21, K3, Z15                            // 6251d5435ef9
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 410.5K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/arm/a.out.go

    	AFMULSD
    	AFNMULSF
    	AFNMULSD
    	ADIVF
    	ADIVD
    	ASQRTF
    	ASQRTD
    	AABSF
    	AABSD
    	ANEGF
    	ANEGD
    
    	ASRL
    	ASRA
    	ASLL
    	AMULU
    	ADIVU
    	AMUL
    	AMMUL
    	ADIV
    	AMOD
    	AMODU
    	ADIVHW
    	ADIVUHW
    
    	AMOVB
    	AMOVBS
    	AMOVBU
    	AMOVH
    	AMOVHS
    	AMOVHU
    	AMOVW
    	AMOVM
    	ASWPBU
    	ASWPW
    
    	ARFE
    	ASWI
    	AMULA
    	AMULS
    	AMMULA
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 05 16:22:12 UTC 2021
    - 7K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/loong64/a.out.go

    	ACMPGTF // ACMPGTF -> fcmp.slt.s
    
    	ALU12IW
    	ALU32ID
    	ALU52ID
    	APCALAU12I
    	APCADDU12I
    	AJIRL
    	ABGE
    	ABLT
    	ABLTU
    	ABGEU
    
    	ADIV
    	ADIVD
    	ADIVF
    	ADIVU
    	ADIVW
    
    	ALL
    	ALLV
    
    	ALUI
    
    	AMOVB
    	AMOVBU
    
    	AMOVD
    	AMOVDF
    	AMOVDW
    	AMOVF
    	AMOVFD
    	AMOVFW
    
    	AMOVH
    	AMOVHU
    	AMOVW
    
    	AMOVWD
    	AMOVWF
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 5.7K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/mips/a.out.go

    	ABLTZAL
    	ABNE
    	ABREAK
    	ACLO
    	ACLZ
    	ACMOVF
    	ACMOVN
    	ACMOVT
    	ACMOVZ
    	ACMPEQD
    	ACMPEQF
    	ACMPGED
    	ACMPGEF
    	ACMPGTD
    	ACMPGTF
    	ADIV
    	ADIVD
    	ADIVF
    	ADIVU
    	ADIVW
    	AGOK
    	ALL
    	ALLV
    	ALUI
    	AMADD
    	AMOVB
    	AMOVBU
    	AMOVD
    	AMOVDF
    	AMOVDW
    	AMOVF
    	AMOVFD
    	AMOVFW
    	AMOVH
    	AMOVHU
    	AMOVW
    	AMOVWD
    	AMOVWF
    	AMOVWL
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 7.6K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/riscv/anames.go

    	"SLLIW",
    	"SRLIW",
    	"SRAIW",
    	"ADDW",
    	"SLLW",
    	"SRLW",
    	"SUBW",
    	"SRAW",
    	"LD",
    	"SD",
    	"MUL",
    	"MULH",
    	"MULHU",
    	"MULHSU",
    	"MULW",
    	"DIV",
    	"DIVU",
    	"REM",
    	"REMU",
    	"DIVW",
    	"DIVUW",
    	"REMW",
    	"REMUW",
    	"LRD",
    	"SCD",
    	"LRW",
    	"SCW",
    	"AMOSWAPD",
    	"AMOADDD",
    	"AMOANDD",
    	"AMOORD",
    	"AMOXORD",
    	"AMOMAXD",
    	"AMOMAXUD",
    	"AMOMIND",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  10. src/runtime/vlop_arm.s

    	CMN 	RM, Rr // t = r-d
    	SUB.CS	RM, Rr, Rr // if (t<-d || t>=0) r=r+d
    	ADD.CC	$1, Rq
    	ADD.PL	RM<<1, Rr
    	ADD.PL	$2, Rq
    	RET
    
    // use hardware divider
    udiv_hardware:
    	DIVUHW	Rq, Rr, Rs
    	MUL	Rs, Rq, RM
    	RSB	Rr, RM, Rr
    	MOVW	Rs, Rq
    	RET
    
    udiv_by_large_d:
    	// at this point we know d>=2^(31-6)=2^25
    	SUB 	$4, Ra, Ra
    	RSB 	$0, Rs, Rs
    	MOVW	Ra>>Rs, Rq
    	MULLU	Rq, Rr, (Rq,Rs)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Jun 04 07:25:06 UTC 2020
    - 7.1K bytes
    - Viewed (0)
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