ADDSW	$0xff, R6, RSP                                   // ERROR "illegal destination register"
	ADDSW	$0xffff0, R6, RSP                                // ERROR "illegal destination register"
	ADDSW	$0x1000100010001000, R6, RSP                     // ERROR "illegal destination register"
	ADDSW	$0x10001000100011, R6, RSP                       // ERROR "illegal destination register"

package arm64

import "cmd/internal/obj"

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADC",
	"ADCS",
	"ADCSW",
	"ADCW",
	"ADD",
	"ADDS",
	"ADDSW",
	"ADDW",
	"ADR",
	"ADRP",
	"AESD",
	"AESE",
	"AESIMC",
	"AESMC",
	"AND",
	"ANDS",
	"ANDSW",
	"ANDW",
	"ASR",
	"ASRW",
	"AT",
	"BCC",
	"BCS",
	"BEQ",
	"BFI",
	"BFIW",

	ADD R25<<54, R17, R16                      // 30da198b
	ADDSW R12.SXTX<<1, R29, R7                 // a7e72c2b
	ADDS R24.UXTX<<4, R25, R21                 // 357338ab
	ADDSW $(3525<<12), R3, R11                 // ADDSW $14438400, R3, R11          // 6b147731
	ADDS $(3525<<12), R3, R11                  // ADDS $14438400, R3, R11           // 6b1477b1
	ADDSW R7->22, R14, R13                     // cd59872b

Extended registers are written as <Rm>{.<extend>{<<<amount>}}.
<extend> can be UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW or SXTX.

Examples:

	ADDS R19.UXTB<<4, R9, R26     <=>    adds x26, x9, w19, uxtb #4
	ADDSW R14.SXTX, R14, R6       <=>    adds w6, w14, w14, sxtx

Memory references: [<Xn|SP>{,#0}] is written as (Rn|RSP), a base register and an immediate

	ADD	R2.SXTX<<1, RSP, RSP            // ffe7228b
	ADD	ZR.SXTX<<1, R2, R3              // 43e43f8b
	ADDW	R2.SXTW, R10, R12               // 4cc1220b
	ADD	R19.UXTX, R14, R17              // d161338b
	ADDSW	R19.UXTW, R14, R17              // d141332b
	ADDS	R12.SXTX, R3, R1                // 61e02cab
	SUB	R19.UXTH<<4, R2, R21            // 553033cb
	SUBW	R1.UXTX<<1, R3, R2              // 6264214b