AESMC	B7.B16, B7.B16

#define aesrndlastx8(K) \
	AESE	K.B16, B0.B16    \
	AESE	K.B16, B1.B16    \
	AESE	K.B16, B2.B16    \
	AESE	K.B16, B3.B16    \
	AESE	K.B16, B4.B16    \
	AESE	K.B16, B5.B16    \
	AESE	K.B16, B6.B16    \
	AESE	K.B16, B7.B16

	MOVD	productTable+0(FP), pTbl
	MOVD	dst+8(FP), dstPtr
	MOVD	src_base+32(FP), srcPtr
	MOVD	src_len+40(FP), srcPtrLen
	MOVD	ctr+56(FP), ctrPtr

	AESE	V0.B16,	 V8.B16
	AESMC	V8.B16,  V8.B16
	AESE	V1.B16,	 V9.B16
	AESMC	V9.B16,  V9.B16
	AESE	V2.B16, V10.B16
	AESMC	V10.B16,  V10.B16
	AESE	V3.B16, V11.B16
	AESMC	V11.B16,  V11.B16
	AESE	V4.B16, V12.B16
	AESMC	V12.B16,  V12.B16
	AESE	V5.B16, V13.B16
	AESMC	V13.B16,  V13.B16
	AESE	V6.B16, V14.B16
	AESMC	V14.B16,  V14.B16
	AESE	V7.B16, V15.B16
	AESMC	V15.B16,  V15.B16

	AESE	V0.B16,	 V8.B16

	AESE	V5.B16, V0.B16
	AESMC	V0.B16, V0.B16
	AESE	V6.B16, V0.B16
	AESMC	V0.B16, V0.B16
	AESE	V7.B16, V0.B16
	AESMC	V0.B16, V0.B16
	AESE	V8.B16, V0.B16
	AESMC	V0.B16, V0.B16
	AESE	V9.B16, V0.B16
	AESMC	V0.B16, V0.B16
	AESE	V10.B16, V0.B16
	AESMC	V0.B16, V0.B16
	AESE	V11.B16, V0.B16
	AESMC	V0.B16, V0.B16
	AESE	V12.B16, V0.B16
	AESMC	V0.B16, V0.B16
	AESE	V13.B16, V0.B16
	AESMC	V0.B16, V0.B16

package arm64

import "cmd/internal/obj"

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADC",
	"ADCS",
	"ADCSW",
	"ADCW",
	"ADD",
	"ADDS",
	"ADDSW",
	"ADDW",
	"ADR",
	"ADRP",
	"AESD",
	"AESE",
	"AESIMC",
	"AESMC",
	"AND",
	"ANDS",
	"ANDSW",
	"ANDW",
	"ASR",
	"ASRW",
	"AT",
	"BCC",
	"BCS",
	"BEQ",
	"BFI",
	"BFIW",
	"BFM",
	"BFMW",
	"BFXIL",
	"BFXILW",
	"BGE",

}

type Goarm64Features struct {
	Version string
	// Large Systems Extension
	LSE bool
	// ARM v8.0 Cryptographic Extension. It includes the following features:
	// * FEAT_AES, which includes the AESD and AESE instructions.
	// * FEAT_PMULL, which includes the PMULL, PMULL2 instructions.
	// * FEAT_SHA1, which includes the SHA1* instructions.
	// * FEAT_SHA256, which includes the SHA256* instructions.
	Crypto bool
}

	DC	IVAC                                             // ERROR "missing register at operand 2"
	AESD	V1.B8, V2.B8                                     // ERROR "invalid arrangement"
	AESE	V1.D2, V2.D2                                     // ERROR "invalid arrangement"
	AESIMC	V1.S4, V2.S4                                     // ERROR "invalid arrangement"

		op += " " + strings.Join(args, ", ")
	}

	return op
}

// No need add "W" to opcode suffix.
// Opcode must be inserted in ascending order.
var noSuffixOpSet = strings.Fields(`
AESD
AESE
AESIMC
AESMC
CRC32B
CRC32CB
CRC32CH
CRC32CW
CRC32CX
CRC32H
CRC32W
CRC32X
LDARB
LDARH
LDAXRB
LDAXRH
LDTRH
LDXRB
LDXRH
SHA1C
SHA1H
SHA1M
SHA1P

	ADD:       "ADD",
	ADDHN:     "ADDHN",
	ADDHN2:    "ADDHN2",
	ADDP:      "ADDP",
	ADDS:      "ADDS",
	ADDV:      "ADDV",
	ADR:       "ADR",
	ADRP:      "ADRP",
	AESD:      "AESD",
	AESE:      "AESE",
	AESIMC:    "AESIMC",
	AESMC:     "AESMC",
	AND:       "AND",
	ANDS:      "ANDS",
	ASR:       "ASR",
	ASRV:      "ASRV",
	AT:        "AT",
	B:         "B",
	BFI:       "BFI",

	VADDP V7.H8, V25.H8, V17.H8                                 // 31bf674e
	VADDV V3.H8, V0                                             // 60b8714e
	AESD V22.B16, V19.B16                                       // d35a284e
	AESE V31.B16, V29.B16                                       // fd4b284e
	AESIMC V12.B16, V27.B16                                     // 9b79284e
	AESMC V14.B16, V28.B16                                      // dc69284e

{"Name":"AESD","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESD <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
{"Name":"AESE","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESE <Vd>.16B, <Vn>.16B","Code":"","Alias":""},