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Results 1 - 7 of 7 for arrangement (0.29 sec)

  1. src/cmd/asm/internal/arch/loong64.go

    		case loong64.LSX:
    			arng_type, ok = loong64LsxArngExtMap[ext]
    			if !ok {
    				return errors.New("Loong64 extension: invalid LSX arrangement type: " + ext)
    			}
    
    		case loong64.LASX:
    			arng_type, ok = loong64LasxArngExtMap[ext]
    			if !ok {
    				return errors.New("Loong64 extension: invalid LASX arrangement type: " + ext)
    			}
    		}
    
    		a.Reg = loong64.REG_ARNG
    		a.Reg += ((reg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT)
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 05 17:31:25 UTC 2025
    - 3.8K bytes
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  2. src/cmd/asm/internal/asm/testdata/arm64error.s

    	VFMLA	V1.B16, V12.B16, V3.B16                          // ERROR "invalid arrangement"
    	VFMLA	V1.H4, V12.H4, V3.H4                             // ERROR "invalid arrangement"
    	VFMLA	V1.H8, V12.H8, V3.H8                             // ERROR "invalid arrangement"
    	VFMLA	V1.H4, V12.H4, V3.H4                             // ERROR "invalid arrangement"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 37.9K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/arch/arm64.go

    	case "D2":
    		curSize = 3
    		curQ = 1
    	default:
    		return 0, errors.New("invalid arrangement in ARM64 register list")
    	}
    	return (int64(curQ) & 1 << 30) | (int64(curSize&3) << 10), nil
    }
    
    // ARM64RegisterListOffset generates offset encoding according to AArch64 specification.
    func ARM64RegisterListOffset(firstReg, regCnt int, arrangement int64) (int64, error) {
    	offset := int64(firstReg)
    	switch regCnt {
    	case 1:
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Feb 14 15:13:11 UTC 2025
    - 10.3K bytes
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  4. src/cmd/asm/internal/asm/parse.go

    			if err != nil {
    				p.errorf("%v", err)
    			}
    			if firstReg == -1 {
    				// only record the first register and arrangement
    				firstReg = int(reg)
    				nextReg = firstReg
    				arrangement = curArrangement
    			} else if curArrangement != arrangement {
    				p.errorf("inconsistent arrangement in ARM64 register list")
    			} else if nextReg != int(reg) {
    				p.errorf("incontiguous register in ARM64 register list: %s", name)
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Feb 14 15:13:11 UTC 2025
    - 37.3K bytes
    - Viewed (0)
  5. LICENSE

    in a country, would infringe one or more identifiable patents in that
    country that you have reason to believe are valid.
    
      If, pursuant to or in connection with a single transaction or
    arrangement, you convey, or propagate by procuring conveyance of, a
    covered work, and grant a patent license to some of the parties
    receiving the covered work authorizing them to use, propagate, modify
    Registered: Sun Sep 07 19:28:11 UTC 2025
    - Last Modified: Fri Apr 23 18:58:53 UTC 2021
    - 33.7K bytes
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  6. CREDITS

    in a country, would infringe one or more identifiable patents in that
    country that you have reason to believe are valid.
    
      If, pursuant to or in connection with a single transaction or
    arrangement, you convey, or propagate by procuring conveyance of, a
    covered work, and grant a patent license to some of the parties
    receiving the covered work authorizing them to use, propagate, modify
    Registered: Sun Sep 07 19:28:11 UTC 2025
    - Last Modified: Thu Mar 13 05:29:51 UTC 2025
    - 1.8M bytes
    - Viewed (0)
  7. docs/LICENSE

    
    Section 7 -- Other Terms and Conditions.
    
      a. The Licensor shall not be bound by any additional or different
         terms or conditions communicated by You unless expressly agreed.
    
      b. Any arrangements, understandings, or agreements regarding the
         Licensed Material not stated herein are separate from and
         independent of the terms and conditions of this Public License.
    
    
    Section 8 -- Interpretation.
    
    Registered: Sun Sep 07 19:28:11 UTC 2025
    - Last Modified: Mon May 10 16:50:06 UTC 2021
    - 18.2K bytes
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