NEG	R0, R4
	ANDS	$15, R4, R4
	// Try zeroing using zva if the start address is aligned with 16
	BEQ	try_zva

	// Non-aligned store
	STP	(ZR, ZR), (R0)
	// Make the destination aligned
	SUB	R4, R1, R1
	ADD	R4, R0, R0
	B	try_zva

tail_maybe_long:
	CMP	$64, R1
	BHS	no_zva

tail63:
	ANDS	$48, R1, R3
	BEQ	last16
	CMPW	$32, R3
	BEQ	last48
	BLT	last32

					lits = append(lits, lit)
				default:
					return nil, errComplex
				}
			}
			ands = append(ands, lits)
		}
		split = append(split, ands)
	}

	// If all the ORs have length 1 (no actual OR'ing going on),
	// push the top-level ANDs to the bottom level, so that we get
	// one // +build line instead of many.
	maxOr := 0
	for _, or := range split {
		if maxOr < len(or) {
			maxOr = len(or)

TEXT countbytebody<>(SB),NOSPLIT,$0
	// R11 = count of byte to search
	MOVD	$0, R11
	// short path to handle 0-byte case
	CBZ	R2, done
	CMP	$0x20, R2
	// jump directly to tail if length < 32
	BLO	tail
	ANDS	$0x1f, R0, R9
	BEQ	chunk
	// Work with not 32-byte aligned head
	BIC	$0x1f, R0, R3
	ADD	$0x20, R3
	PCALIGN $16
head_loop:
	MOVBU.P	1(R0), R5
	CMP	R5, R1
	CINC	EQ, R11, R11
	SUB	$1, R2, R2
	CMP	R0, R3

	TST $7, R2                                 // 5f0840f2
	ANDS R2, R0, ZR                            // 1f0002ea
	ANDS $7, R2, ZR                            // 5f0840f2
	ANDSW $2863311530, R24, ZR                 // 1ff30172
	ANDSW $2863311530, R24, R23                // 17f30172
	ANDS $-140737488289793, R2, R5             // 458051f2
	ANDSW R26->24, R21, R15                    // af629a6a
	ANDS R30@>44, R3, R26                      // 7ab0deea

	LDP	4*16(a_ptr), (acc0, acc1)// iff select[0] == 0, z3 = z1
	LDP	5*16(a_ptr), (acc2, acc3)
	ANDS	$1, hlp1, ZR
	CSEL	EQ, acc0, y0, y0
	CSEL	EQ, acc1, y1, y1
	CSEL	EQ, acc2, y2, y2
	CSEL	EQ, acc3, y3, y3
	LDP	p256one<>+0x00(SB), (acc0, acc1)
	LDP	p256one<>+0x10(SB), (acc2, acc3)
	ANDS	$2, hlp1, ZR            // iff select[1] == 0, z3 = 1
	CSEL	EQ, acc0, y0, y0
	CSEL	EQ, acc1, y1, y1

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADC",
	"ADCS",
	"ADCSW",
	"ADCW",
	"ADD",
	"ADDS",
	"ADDSW",
	"ADDW",
	"ADR",
	"ADRP",
	"AESD",
	"AESE",
	"AESIMC",
	"AESMC",
	"AND",
	"ANDS",
	"ANDSW",
	"ANDW",
	"ASR",
	"ASRW",
	"AT",
	"BCC",
	"BCS",
	"BEQ",
	"BFI",
	"BFIW",
	"BFM",
	"BFMW",
	"BFXIL",
	"BFXILW",
	"BGE",
	"BGT",
	"BHI",
	"BHS",
	"BIC",

	// Different bytes have different bit masks (i.e: 1, 4, 16, 64)
	MOVD	$0x40100401, R5
	VMOV	R1, V0.B16
	// Work with aligned 32-byte chunks
	BIC	$0x1f, R0, R3
	VMOV	R5, V5.S4
	ANDS	$0x1f, R0, R9
	AND	$0x1f, R2, R10
	BEQ	loop

	// Input string is not 32-byte aligned. We calculate the
	// syndrome value for the aligned 32 bytes block containing
	// the first bytes and mask off the irrelevant part.

	// ANDS <Wd>, <Wn>, #<imm>
	{0xffc00000, 0x72000000, ANDS, instArgs{arg_Wd, arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil},
	// TST <Xn>, #<imm>
	{0xff80001f, 0xf200001f, TST, instArgs{arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil},
	// ANDS <Xd>, <Xn>, #<imm>
	{0xff800000, 0xf2000000, ANDS, instArgs{arg_Xd, arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil},

	AND	$0xff00ffff, R1                     // AND	$4278255615, R1                 // fbff9fd21be0bff221001b8a
	ANDS	$0xffff, R2                         // ANDS	$65535, R2                      // 423c40f2
	AND	$0x7fffffff, R3                     // AND	$2147483647, R3                 // 63784092
	ANDS	$0x0ffffffff80000000, R2            // ANDS	$-2147483648, R2                // 428061f2

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

TEXT errors(SB),$0
	AND	$1, RSP                                          // ERROR "illegal source register"
	ANDS	$1, R0, RSP                                      // ERROR "illegal combination"
	ADDSW	R7->32, R14, R13                                 // ERROR "shift amount out of range 0 to 31"