VLD1.P	48(R10), [V13.B16, V14.B16, V15.B16]
	AESD	V5.B16, V0.B16
	AESIMC	V0.B16, V0.B16
	AESD	V6.B16, V0.B16
	AESIMC	V0.B16, V0.B16
	AESD	V7.B16, V0.B16
	AESIMC	V0.B16, V0.B16
	AESD	V8.B16, V0.B16
	AESIMC	V0.B16, V0.B16
	AESD	V9.B16, V0.B16
	AESIMC	V0.B16, V0.B16
	AESD	V10.B16, V0.B16
	AESIMC	V0.B16, V0.B16
	AESD	V11.B16, V0.B16
	AESIMC	V0.B16, V0.B16
	AESD	V12.B16, V0.B16
	AESIMC	V0.B16, V0.B16

package arm64

import "cmd/internal/obj"

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADC",
	"ADCS",
	"ADCSW",
	"ADCW",
	"ADD",
	"ADDS",
	"ADDSW",
	"ADDW",
	"ADR",
	"ADRP",
	"AESD",
	"AESE",
	"AESIMC",
	"AESMC",
	"AND",
	"ANDS",
	"ANDSW",
	"ANDW",
	"ASR",
	"ASRW",
	"AT",
	"BCC",
	"BCS",
	"BEQ",
	"BFI",
	"BFIW",
	"BFM",
	"BFMW",
	"BFXIL",
	"BFXILW",

	VADD V5.H8, V18.H8, V9.H8         <=>      add v9.8h, v18.8h, v5.8h
	VLD1.P (R6)(R11), [V31.D1]        <=>      ld1 {v31.1d}, [x6], x11
	VFMLA V29.S2, V20.S2, V14.S2      <=>      fmla v14.2s, v20.2s, v29.2s
	AESD V22.B16, V19.B16             <=>      aesd v19.16b, v22.16b
	SCVTFWS R3, F16                   <=>      scvtf s17, w6

6. Align directive

Go asm supports the PCALIGN directive, which indicates that the next instruction should be aligned

	return
}

type Goarm64Features struct {
	Version string
	// Large Systems Extension
	LSE bool
	// ARM v8.0 Cryptographic Extension. It includes the following features:
	// * FEAT_AES, which includes the AESD and AESE instructions.
	// * FEAT_PMULL, which includes the PMULL, PMULL2 instructions.
	// * FEAT_SHA1, which includes the SHA1* instructions.
	// * FEAT_SHA256, which includes the SHA256* instructions.
	Crypto bool
}

	if args != nil {
		op += " " + strings.Join(args, ", ")
	}

	return op
}

// No need add "W" to opcode suffix.
// Opcode must be inserted in ascending order.
var noSuffixOpSet = strings.Fields(`
AESD
AESE
AESIMC
AESMC
CRC32B
CRC32CB
CRC32CH
CRC32CW
CRC32CX
CRC32H
CRC32W
CRC32X
LDARB
LDARH
LDAXRB
LDAXRH
LDTRH
LDXRB
LDXRH
SHA1C
SHA1H
SHA1M

	ADCS:      "ADCS",
	ADD:       "ADD",
	ADDHN:     "ADDHN",
	ADDHN2:    "ADDHN2",
	ADDP:      "ADDP",
	ADDS:      "ADDS",
	ADDV:      "ADDV",
	ADR:       "ADR",
	ADRP:      "ADRP",
	AESD:      "AESD",
	AESE:      "AESE",
	AESIMC:    "AESIMC",
	AESMC:     "AESMC",
	AND:       "AND",
	ANDS:      "ANDS",
	ASR:       "ASR",
	ASRV:      "ASRV",
	AT:        "AT",
	B:         "B",

	DC	VAE1IS, R0                                       // ERROR "illegal argument"
	DC	IVAC                                             // ERROR "missing register at operand 2"
	AESD	V1.B8, V2.B8                                     // ERROR "invalid arrangement"
	AESE	V1.D2, V2.D2                                     // ERROR "invalid arrangement"

	VADD V5.H8, V18.H8, V9.H8                                   // 4986654e
	VADDP V7.H8, V25.H8, V17.H8                                 // 31bf674e
	VADDV V3.H8, V0                                             // 60b8714e
	AESD V22.B16, V19.B16                                       // d35a284e
	AESE V31.B16, V29.B16                                       // fd4b284e
	AESIMC V12.B16, V27.B16                                     // 9b79284e

{"Name":"ADDV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ADDV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"AESD","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESD <Vd>.16B, <Vn>.16B","Code":"","Alias":""},