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Results 1 - 6 of 6 for R26 (0.03 sec)

  1. src/cmd/asm/internal/asm/testdata/mips64.s

    	ADD	$-7193, R24	// 2318e3e7
    	ADDV	$-7193, R24	// 6318e3e7
    
    //	LSUBW rreg ',' sreg ',' rreg
    //	{
    //		outcode(int($1), &$2, int($4), &$6);
    //	}
    	SUB	R6, R26, R27	// 0346d822
    	SUBU	R6, R26, R27	// 0346d823
    	SUBV	R16, R17, R26	// 0230d02e
    	SUBVU	R16, R17, R26	// 0230d02f
    
    //	LSUBW imm ',' sreg ',' rreg
    //	{
    //		outcode(int($1), &$2, int($4), &$6);
    //	}
    	SUB	$-3126, R17, R22	// 22360c36
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/operand_test.go

    	{"R16", "R16"},
    	{"R17", "R17"},
    	{"R18", "R18"},
    	{"R19", "R19"},
    	{"R2", "R2"},
    	{"R20", "R20"},
    	{"R21", "R21"},
    	{"R22", "R22"},
    	{"R23", "R23"},
    	{"R24", "R24"},
    	{"R25", "R25"},
    	{"R26", "R26"},
    	{"R27", "R27"},
    	{"R28", "R28"},
    	{"R29", "R29"},
    	{"R3", "R3"},
    	{"R31", "R31"},
    	{"R4", "R4"},
    	{"R5", "R5"},
    	{"R6", "R6"},
    	{"R7", "R7"},
    	{"R8", "R8"},
    	{"R9", "R9"},
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 29 18:31:05 UTC 2023
    - 23.9K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	AND $-9223372036854775808, R1, R1          // 21004192
    	ANDW $4026540031, R29, R2                  // a2430412
    	AND $34903429696192636, R12, R19           // 93910e92
    	ANDW R9@>7, R19, R26                       // 7a1ec90a
    	AND R9@>7, R19, R26                        // 7a1ec98a
    	TSTW $2863311530, R24                      // 1ff30172
    	TST R2, R0                                 // 1f0002ea
    	TST $7, R2                                 // 5f0840f2
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64.s

    	MSR	R2, CNTV_CTL_EL0                   // 22e31bd5
    	MRS	CNTV_CVAL_EL0, R8                  // 48e33bd5
    	MSR	R26, CNTV_CVAL_EL0                 // 5ae31bd5
    	MRS	CNTV_TVAL_EL0, R6                  // 06e33bd5
    	MSR	R19, CNTV_TVAL_EL0                 // 13e31bd5
    	MRS	CNTKCTL_EL1, R16                   // 10e138d5
    	MSR	R26, CNTKCTL_EL1                   // 1ae118d5
    	MRS	CNTPCT_EL0, R9                     // 29e03bd5
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 95.3K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/arm64error.s

    	STP	(R3, R4), 0x1234567(R27)                         // ERROR "REGTMP used in large offset store"
    	LDP	0x1234567(R27), (R3, R4)                         // ERROR "REGTMP used in large offset load"
    	STP	(R26, R27), 700(R2)                              // ERROR "cannot use REGTMP as source"
    	MOVK	$0, R10                                          // ERROR "zero shifts cannot be handled correctly"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 37.9K bytes
    - Viewed (0)
  6. lib/fips140/v1.0.0.zip

    + z[2] ADDV R18, R7, R11 // z_lo[2] = x[2] * y + z[2] + c SGTU R18, R11, R19 ADDV R25, R19, R7 // next c MULHVU R16, R5, R26 // z_hi[3] = x[3] * y MULV R16, R5, R16 // z_lo[3] = x[3] * y ADDV R16, R12, R18 // z_lo[3] = x[3] * y + z[3] SGTU R16, R18, R19 ADDV R26, R19, R26 // z_hi[3] = x[3] * y + z[3] ADDV R18, R7, R12 // z_lo[3] = x[3] * y + z[3] + c SGTU R18, R12, R19 ADDV R26, R19, R7 // next c MOVV R9, 0*8(R4) // z[0] MOVV R10, 1*8(R4) // z[1] MOVV R11, 2*8(R4) // z[2] MOVV R12, 3*8(R4) // z[3]...
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Jan 29 15:10:35 UTC 2025
    - 635K bytes
    - Viewed (0)
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