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Results 1 - 6 of 6 for R23 (0.03 sec)
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src/cmd/asm/internal/asm/testdata/mips64.s
SC R1, (R2) // e0410000 // LMOVH rreg ',' addr // { // outcode(int($1), &$2, 0, &$4); // } MOVH R13, (R7) // a4ed0000 MOVH R10, 61(R23) // a6ea003d MOVH R8, -33(R12) // a588ffdf MOVHU R13, (R7) // a4ed0000 MOVHU R10, 61(R23) // a6ea003d MOVHU R8, -33(R12) // a588ffdf // LMOVB rreg ',' addr // { // outcode(int($1), &$2, 0, &$4); // } MOVB R1, foo<>+3(SB)
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
MSR R14, PMEVCNTR29_EL0 // aeeb1bd5 MSR R23, PMEVCNTR30_EL0 // d7eb1bd5 MRS PMEVTYPER0_EL0, R23 // 17ec3bd5 MRS PMEVTYPER1_EL0, R30 // 3eec3bd5 MRS PMEVTYPER2_EL0, R12 // 4cec3bd5 MRS PMEVTYPER3_EL0, R13 // 6dec3bd5 MRS PMEVTYPER4_EL0, R25 // 99ec3bd5 MRS PMEVTYPER5_EL0, R23 // b7ec3bd5
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 95.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/operand_test.go
{"R13", "R13"}, {"R14", "R14"}, {"R15", "R15"}, {"R16", "R16"}, {"R17", "R17"}, {"R18", "R18"}, {"R19", "R19"}, {"R2", "R2"}, {"R20", "R20"}, {"R21", "R21"}, {"R22", "R22"}, {"R23", "R23"}, {"R24", "R24"}, {"R25", "R25"}, {"R26", "R26"}, {"R27", "R27"}, {"R28", "R28"}, {"R29", "R29"}, {"R3", "R3"}, {"R31", "R31"}, {"R4", "R4"}, {"R5", "R5"}, {"R6", "R6"},
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 29 18:31:05 UTC 2023 - 23.9K bytes - Viewed (0) -
doc/asm.html
General purpose registers are named <code>R0</code> through <code>R31</code>, floating point registers are <code>F0</code> through <code>F31</code>. </p> <p> <code>R30</code> is reserved to point to <code>g</code>. <code>R23</code> is used as a temporary register. </p> <p> In a <code>TEXT</code> directive, the frame size <code>$-4</code> for MIPS or <code>$-8</code> for MIPS64 instructs the linker not to save <code>LR</code>. </p>
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (0) -
lib/fips140/v1.0.0.zip
acc5 R8 #define acc6 R9 #define acc7 R10 #define t0 R11 #define t1 R12 #define t2 R13 #define t3 R14 #define const0 R15 #define const1 R16 #define hlp0 R17 #define hlp1 res_ptr #define x0 R19 #define x1 R20 #define x2 R21 #define x3 R22 #define y0 R23 #define y1 R24 #define y2 R25 #define y3 R26 #define const2 t2 #define const3 t3 DATA p256const0<>+0x00(SB)/8, $0x00000000ffffffff DATA p256const1<>+0x00(SB)/8, $0xffffffff00000001 DATA p256ordK0<>+0x00(SB)/8, $0xccd1c8aaee00bc4f DATA p256ord<>+0x00(SB)/8,...
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Jan 29 15:10:35 UTC 2025 - 635K bytes - Viewed (0)