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Results 1 - 10 of 16 for ROL (0.16 sec)
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src/internal/chacha8rand/chacha8_amd64.s
// See chacha8_generic.go for additional details. // ROL rotates the uint32s in register R left by N bits, using temporary T. #define ROL(N, R, T) \ MOVO R, T; PSLLL $(N), T; PSRLL $(32-(N)), R; PXOR T, R // ROL16 rotates the uint32s in register R left by 16, using temporary T if needed. #ifdef GOAMD64_v2 #define ROL16(R, T) PSHUFB ·rol16<>(SB), R #else #define ROL16(R, T) ROL(16, R, T) #endif
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Dec 05 20:34:30 UTC 2023 - 4.6K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
SEXTH X17, X18 // 13995860 XNOR X18, X19, X20 // 33ca2941 XNOR X18, X19 // b3c92941 ZEXTH X19, X20 // 3bca0908 // 1.3: Bitwise Rotation (Zbb) ROL X8, X9, X10 // 33958460 or b30f8040b3dff4013395840033e5af00 ROL X8, X9 // b3948460 or b30f8040b3dff401b3948400b3e49f00 ROLW X9, X10, X11 // bb159560 or b30f9040bb5ff501bb159500b3e5bf00 ROLW X9, X10 // 3b159560 or b30f9040bb5ff5013b15950033e5af00
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
test/codegen/rotate.go
func rot64nc(x uint64, z uint) uint64 { var a uint64 z &= 63 // amd64:"ROLQ",-"AND" // arm64:"ROR","NEG",-"AND" // ppc64x:"ROTL",-"NEG",-"AND" // loong64: "ROTRV", -"AND" // riscv64: "ROL",-"AND" a += x<<z | x>>(64-z) // amd64:"RORQ",-"AND" // arm64:"ROR",-"NEG",-"AND" // ppc64x:"ROTL","NEG",-"AND" // loong64: "ROTRV", -"AND" // riscv64: "ROR",-"AND" a += x>>z | x<<(64-z)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 6K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/plan9x.go
NOT: true, OR: true, OUT: true, POP: true, POPA: true, POPCNT: true, PUSH: true, PUSHA: true, RCL: true, RCR: true, ROL: true, ROR: true, SAR: true, SBB: true, SHL: true, SHLD: true, SHR: true, SHRD: true, SUB: true, TEST: true, XADD: true,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jul 12 20:38:21 UTC 2023 - 7.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
(RotateLeft16 <t> x y) => (OR (SLL <t> x (ANDI [15] <y.Type> y)) (SRL <t> (ZeroExt16to64 x) (ANDI [15] <y.Type> (NEG <y.Type> y)))) (RotateLeft32 ...) => (ROLW ...) (RotateLeft64 ...) => (ROL ...) (Less64 ...) => (SLT ...) (Less32 x y) => (SLT (SignExt32to64 x) (SignExt32to64 y)) (Less16 x y) => (SLT (SignExt16to64 x) (SignExt16to64 y)) (Less8 x y) => (SLT (SignExt8to64 x) (SignExt8to64 y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0 | arg1 {name: "ORI", argLength: 1, reg: gp11, asm: "ORI", aux: "Int64"}, // arg0 | auxint {name: "ROL", argLength: 2, reg: gp21, asm: "ROL"}, // rotate left arg0 by (arg1 & 63) {name: "ROLW", argLength: 2, reg: gp21, asm: "ROLW"}, // rotate left least significant word of arg0 by (arg1 & 31), sign extended
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/tables.go
/*10528*/ uint16(xSetOp), uint16(ROL), /*10530*/ uint16(xReadIb), /*10531*/ uint16(xArgRM16), /*10532*/ uint16(xArgImm8u), /*10533*/ uint16(xMatch), /*10534*/ uint16(xSetOp), uint16(ROL), /*10536*/ uint16(xReadIb), /*10537*/ uint16(xArgRM32), /*10538*/ uint16(xArgImm8u), /*10539*/ uint16(xMatch), /*10540*/ uint16(xSetOp), uint16(ROL), /*10542*/ uint16(xReadIb),
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 16 22:24:28 UTC 2022 - 266.8K bytes - Viewed (0) -
src/crypto/sha1/sha1block_amd64.s
VMOVDQU Y0, (OFFSET)(R14) // Message scheduling pre-compute for rounds 32-79 // In SHA-1 specification we have: // w[i] = (w[i-3] ^ w[i-8] ^ w[i-14] ^ w[i-16]) rol 1 // Which is the same as: // w[i] = (w[i-6] ^ w[i-16] ^ w[i-28] ^ w[i-32]) rol 2 // This allows for more efficient vectorization, // since w[i]->w[i-3] dependency is broken #define PRECALC_32_79(REG,REG_SUB_4,REG_SUB_8,REG_SUB_16,REG_SUB_28,K_OFFSET,OFFSET) \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 31.5K bytes - Viewed (0) -
docs/hu/docs/index.md
return {"item_id": item_id, "q": q} ``` **Megjegyzés**: Ha nem tudod, tekintsd meg a _"Sietsz?"_ szekciót <a href="https://fastapi.tiangolo.com/async/#in-a-hurry" target="_blank">`async` és `await`-ről dokumentációba</a>. </details> ### Futtasd le Indítsd el a szervert a következő paranccsal: <div class="termy"> ```console $ uvicorn main:app --reload
Registered: Mon Jun 17 08:32:26 UTC 2024 - Last Modified: Mon Apr 29 05:18:04 UTC 2024 - 20.2K bytes - Viewed (0)