"BDNZ",
	"BDZ",
	"CMP",
	"CMPU",
	"CMPEQB",
	"CNTLZW",
	"CNTLZWCC",
	"CRAND",
	"CRANDN",
	"CREQV",
	"CRNAND",
	"CRNOR",
	"CROR",
	"CRORN",
	"CRXOR",
	"DIVW",
	"DIVWCC",
	"DIVWVCC",
	"DIVWV",
	"DIVWU",
	"DIVWUCC",
	"DIVWUVCC",
	"DIVWUV",
	"MODUD",
	"MODUW",
	"MODSD",
	"MODSW",
	"EQV",
	"EQVCC",
	"EXTSB",
	"EXTSBCC",
	"EXTSH",
	"EXTSHCC",
	"FABS",

// Code generated by stringer -i a.out.go -o anames.go -p s390x; DO NOT EDIT.

package s390x

import "cmd/internal/obj"

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADD",
	"ADDC",
	"ADDE",
	"ADDW",
	"DIVW",
	"DIVWU",
	"DIVD",
	"DIVDU",
	"MODW",
	"MODWU",
	"MODD",
	"MODDU",
	"MULLW",
	"MULLD",
	"MULHD",
	"MULHDU",
	"MLGR",
	"SUB",
	"SUBC",
	"SUBV",
	"SUBE",
	"SUBW",
	"NEG",

	DIVD	R1, R2, R3            // b90400b2b90d00a1b904003b
	DIVW	R4, R5                // b90400b5b91d00a4b904005b
	DIVW	R4, R5, R6            // b90400b5b91d00a4b904006b
	DIVDU	R7, R8                // a7a90000b90400b8b98700a7b904008b
	DIVDU	R7, R8, R9            // a7a90000b90400b8b98700a7b904009b
	DIVWU	R1, R2                // a7a90000b90400b2b99700a1b904002b
	DIVWU	R1, R2, R3            // a7a90000b90400b2b99700a1b904003b

		var r2 Word
		q, r2 = z.divW(u, v[0])
		r = z2.setWord(r2)
		return
	}

	q, r = z.divLarge(z2, u, v)
	return
}

// divW returns q, r such that q = ⌊x/y⌋ and r = x%y = x - q·y.
// It uses z as the storage for q.
// Note that y is a single digit (Word), not a big number.
func (z nat) divW(x nat, y Word) (q nat, r Word) {
	m := len(x)
	switch {
	case y == 0:

	"CMPGEF",
	"CMPGTD",
	"CMPGTF",
	"LU12IW",
	"LU32ID",
	"LU52ID",
	"PCALAU12I",
	"PCADDU12I",
	"JIRL",
	"BGE",
	"BLT",
	"BLTU",
	"BGEU",
	"DIV",
	"DIVD",
	"DIVF",
	"DIVU",
	"DIVW",
	"LL",
	"LLV",
	"LUI",
	"MOVB",
	"MOVBU",
	"MOVD",
	"MOVDF",
	"MOVDW",
	"MOVF",
	"MOVFD",
	"MOVFW",
	"MOVH",
	"MOVHU",
	"MOVW",
	"MOVWD",
	"MOVWF",
	"MOVWL",
	"MOVWR",

	"SLLIW",
	"SRLIW",
	"SRAIW",
	"ADDW",
	"SLLW",
	"SRLW",
	"SUBW",
	"SRAW",
	"LD",
	"SD",
	"MUL",
	"MULH",
	"MULHU",
	"MULHSU",
	"MULW",
	"DIV",
	"DIVU",
	"REM",
	"REMU",
	"DIVW",
	"DIVUW",
	"REMW",
	"REMUW",
	"LRD",
	"SCD",
	"LRW",
	"SCW",
	"AMOSWAPD",
	"AMOADDD",
	"AMOANDD",
	"AMOORD",
	"AMOXORD",
	"AMOMAXD",
	"AMOMAXUD",
	"AMOMIND",
	"AMOMINUD",

	DIVD R3, R4, R5                 // 7ca41bd2
	DIVW R3, R4                     // 7c841bd6
	DIVW R3, R4, R5                 // 7ca41bd6
	DIVDCC R3,R4, R5                // 7ca41bd3
	DIVWCC R3,R4, R5                // 7ca41bd7
	DIVDU R3, R4, R5                // 7ca41b92
	DIVWU R3, R4, R5                // 7ca41b96
	DIVDV R3, R4, R5                // 7ca41fd2
	DIVWV R3, R4, R5                // 7ca41fd6

(Div64 [false] x y) => (DIVD x y)
(Div64u ...) => (DIVDU ...)
(Div32 [false] x y) => (DIVW x y)
(Div32u ...) => (DIVWU ...)
(Div16 [false]  x y) => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
(Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
(Div8 x y) => (DIVW  (SignExt8to32 x) (SignExt8to32 y))
(Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))

(Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...)

(Div64u ...) => (DIVDU ...)
// DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor,
// so a sign/zero extension of the dividend is required.
(Div32  x y) => (DIVW  (MOVWreg x) y)
(Div32u x y) => (DIVWU (MOVWZreg x) y)
(Div16  x y) => (DIVW  (MOVHreg x) (MOVHreg y))
(Div16u x y) => (DIVWU (MOVHZreg x) (MOVHZreg y))
(Div8   x y) => (DIVW  (MOVBreg x) (MOVBreg y))
(Div8u  x y) => (DIVWU (MOVBZreg x) (MOVBZreg y))

		{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"},   // arg0/arg1 (signed 64-bit)
		{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"},   // arg0/arg1 (signed 32-bit)
		{name: "DIVDU", argLength: 2, reg: gp21, asm: "DIVDU", typ: "Int64"}, // arg0/arg1 (unsigned 64-bit)
		{name: "DIVWU", argLength: 2, reg: gp21, asm: "DIVWU", typ: "Int32"}, // arg0/arg1 (unsigned 32-bit)