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src/runtime/memmove_386.s
// // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal // in the Software without restriction, including without limitation the rights // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell // copies of the Software, and to permit persons to whom the Software is // furnished to do so, subject to the following conditions: //
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Nov 06 10:24:44 UTC 2021 - 4.4K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_s390x.go
} //go:nosplit //go:noinline func StoreReluintptr(ptr *uintptr, val uintptr) { *ptr = val } //go:noescape func And8(ptr *uint8, val uint8) //go:noescape func Or8(ptr *uint8, val uint8) // NOTE: Do not add atomicxor8 (XOR is not idempotent). //go:noescape func And(ptr *uint32, val uint32) //go:noescape func Or(ptr *uint32, val uint32) //go:noescape
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 2.5K bytes - Viewed (0) -
src/internal/bytealg/indexbyte_ppc64x.s
BLT cmp1 _LHBEX (R0)(R3),R10 CMPB R10,R5,R10 SLDCC $48,R10,R10 CNTLZD R10,R10 SRD $3,R10,R3 BNE found cmp1: // Length 1 MOVD $-1,R3 ANDCC $1,R4,R31 BEQ found MOVBZ -1(R9),R10 CMPB R10,R5,R10 ANDCC $1,R10 ADD $-1,R4 ISEL CR0EQ,R3,R4,R3 found: RET #endif notfound: MOVD $-1,R3
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:10:29 UTC 2023 - 6.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
POPCNT R3, R4 // b9e10043 AND R1, R2 // b9800021 AND R1, R2, R3 // b9e42031 AND $-2, R1 // a517fffe AND $-65536, R1 // c01bffff0000 AND $1, R1 // c0a100000001b980001a ANDW R1, R2 // 1421 ANDW R1, R2, R3 // b9f42031 ANDW $1, R1 // c01b00000001 ANDW $131071, R1 // a5160001
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/cmd/internal/notsha256/sha256block_amd64.s
RORL $2, DI; \ MOVL a, DX; \ ANDL b, BX; \ RORL $13, DX; \ MOVL a, CX; \ ANDL c, CX; \ XORL DX, DI; \ XORL CX, BX; \ MOVL a, DX; \ MOVL b, CX; \ RORL $22, DX; \ ANDL a, CX; \ XORL CX, BX; \ XORL DX, DI; \ ADDL DI, BX // Calculate T1 and T2, then e = d + T1 and a = T1 + T2. // The values for e and a are stored in d and h, ready for rotation.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 14K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_test.go
N = 1 << 10 } // Set and then clear every bit in the array bit-by-bit in different goroutines. done := make(chan bool) for i := 0; i < 8; i++ { m := uint8(1 << i) go func() { for n := 0; n < N; n++ { for i := range a { atomic.Or8(&a[i], m) if atomic.Load8(&a[i])&m != m { t.Errorf("a[%v] bit %#x not set", i, m) } atomic.And8(&a[i], ^m)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 8.5K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_ppc64x.go
//go:noescape func LoadAcq64(ptr *uint64) uint64 //go:noescape func LoadAcquintptr(ptr *uintptr) uintptr //go:noescape func And8(ptr *uint8, val uint8) //go:noescape func Or8(ptr *uint8, val uint8) // NOTE: Do not add atomicxor8 (XOR is not idempotent). //go:noescape func And(ptr *uint32, val uint32) //go:noescape func Or(ptr *uint32, val uint32) //go:noescape func And32(ptr *uint32, val uint32) uint32
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 2.1K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_riscv64.go
//go:noescape func LoadAcq64(ptr *uint64) uint64 //go:noescape func LoadAcquintptr(ptr *uintptr) uintptr //go:noescape func Or8(ptr *uint8, val uint8) //go:noescape func And8(ptr *uint8, val uint8) //go:noescape func And(ptr *uint32, val uint32) //go:noescape func Or(ptr *uint32, val uint32) //go:noescape func And32(ptr *uint32, val uint32) uint32 //go:noescape
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 2K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_mipsx.s
AND R1, R3 #ifdef GOARCH_mips // Big endian. ptr = ptr ^ 3 XOR $3, R1 #endif AND $3, R1, R4 // R4 = ((ptr & 3) * 8) SLL $3, R4 SLL R4, R2, R2 // Shift val for aligned ptr. R2 = val << R4 SYNC try_or8: LL (R3), R4 // R4 = *R3 OR R2, R4 SC R4, (R3) // *R3 = R4 BEQ R4, try_or8 SYNC RET // void And8(byte volatile*, byte);
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 21:29:34 UTC 2024 - 4.9K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0)