{name: "ADDSconst", argLength: 1, reg: gp11carry, asm: "ADD", aux: "Int32"}, // arg0 + auxInt, set carry flag
		{name: "ADC", argLength: 3, reg: gp2flags1, asm: "ADC", commutative: true},  // arg0 + arg1 + carry, arg2=flags
		{name: "ADCconst", argLength: 2, reg: gp1flags1, asm: "ADC", aux: "Int32"},  // arg0 + auxInt + carry, arg1=flags

	return func(types.UID) {
		//nolint:logcheck
		klog.ErrorS(nil, "DeleteServiceAccountToken unsupported in PersistentVolumeController")
	}
}

func (adc *PersistentVolumeController) GetExec(pluginName string) utilexec.Interface {
	return utilexec.New()
}

func (ctrl *PersistentVolumeController) GetNodeLabels() (map[string]string, error) {

// Code generated by stringer -i a.out.go -o anames.go -p arm64; DO NOT EDIT.

package arm64

import "cmd/internal/obj"

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADC",
	"ADCS",
	"ADCSW",
	"ADCW",
	"ADD",
	"ADDS",
	"ADDSW",
	"ADDW",
	"ADR",
	"ADRP",
	"AESD",
	"AESE",
	"AESIMC",
	"AESMC",
	"AND",
	"ANDS",
	"ANDSW",
	"ANDW",
	"ASR",
	"ASRW",
	"AT",
	"BCC",
	"BCS",
	"BEQ",

	ADC:               "ADC",
	ADC_ZZ:            "ADC.ZZ",
	ADC_S_EQ:          "ADC.S.EQ",
	ADC_S_NE:          "ADC.S.NE",
	ADC_S_CS:          "ADC.S.CS",
	ADC_S_CC:          "ADC.S.CC",
	ADC_S_MI:          "ADC.S.MI",
	ADC_S_PL:          "ADC.S.PL",
	ADC_S_VS:          "ADC.S.VS",
	ADC_S_VC:          "ADC.S.VC",
	ADC_S_HI:          "ADC.S.HI",
	ADC_S_LS:          "ADC.S.LS",

BE	a[bc]d			abd		(0,3)
BE	a[b-d]e			ace		(0,3)
BE	a[b-d]			aac		(1,3)
BE	a[-b]			a-		(0,2)
BE	a[b-]			a-		(0,2)
BE	a]			a]		(0,2)
BE	a[]]b			a]b		(0,3)
BE	a[^bc]d			aed		(0,3)
BE	a[^-b]c			adc		(0,3)
BE	a[^]b]c			adc		(0,3)
E	ab|cd			abc		(0,2)
E	ab|cd			abcd		(0,2)
E	a\(b			a(b		(0,3)
E	a\(*b			ab		(0,2)
E	a\(*b			a((b		(0,4)
E	((a))			abc		(0,1)(0,1)(0,1)
E	(a)b(c)			abc		(0,3)(0,1)(2,3)

# Instructions mnemonics mapping rules

1. Most instructions use width suffixes of instruction names to indicate operand width rather than
using different register names.

Examples:

	ADC R24, R14, R12          <=>     adc x12, x14, x24
	ADDW R26->24, R21, R15     <=>     add w15, w21, w26, asr #24
	FCMPS F2, F3               <=>     fcmp s3, s2
	FCMPD F2, F3               <=>     fcmp d3, d2

	/*8064*/ uint16(xSetOp), uint16(ADC),
	/*8066*/ uint16(xReadSlashR),
	/*8067*/ uint16(xArgRM32),
	/*8068*/ uint16(xArgR32),
	/*8069*/ uint16(xMatch),
	/*8070*/ uint16(xCondDataSize), 8058, 8064, 8074,
	/*8074*/ uint16(xSetOp), uint16(ADC),
	/*8076*/ uint16(xReadSlashR),
	/*8077*/ uint16(xArgRM64),
	/*8078*/ uint16(xArgR64),
	/*8079*/ uint16(xMatch),
	/*8080*/ uint16(xSetOp), uint16(ADC),

	case 0:
		disp = uint64(a.Disp)
	default:
		return "", 0
	}

	s, base := symname(disp)
	return s, int64(disp) - int64(base)
}

var plan9Suffix = [maxOp + 1]bool{
	ADC:       true,
	ADD:       true,
	AND:       true,
	BSF:       true,
	BSR:       true,
	BT:        true,
	BTC:       true,
	BTR:       true,
	BTS:       true,
	CMP:       true,
	CMPXCHG:   true,

	RET

TEXT armXadd64<>(SB),NOSPLIT,$0-20
	// addr is already in R1
	MOVW	delta_lo+4(FP), R2
	MOVW	delta_hi+8(FP), R3

add64loop:
	LDREXD	(R1), R4	// loads R4 and R5
	ADD.S	R2, R4
	ADC	R3, R5

	DMB	MB_ISHST

	STREXD	R4, (R1), R0	// stores R4 and R5
	CMP	$0, R0
	BNE	add64loop

	DMB	MB_ISH

	MOVW	R4, new_lo+12(FP)
	MOVW	R5, new_hi+16(FP)
	RET

	SWI $0

	MOVW 8(R13), R0 // sec.low
	MOVW 12(R13), R4 // sec.high
	MOVW 16(R13), R2 // nsec

	MOVW $1000000000, R3
	MULLU R0, R3, (R1, R0)
	MUL R3, R4
	ADD.S R2, R0
	ADC R4, R1

	MOVW R0, ret_lo+0(FP)
	MOVW R1, ret_hi+4(FP)
	RET

TEXT runtime·asmSigaction(SB),NOSPLIT|NOFRAME,$0
	MOVW sig+0(FP), R0		// arg 1 sig
	MOVW new+4(FP), R1		// arg 2 act