"R10",
	"R11", // REGCTXT for closures
	"R12",
	"R13", // REGTLS
	"R14",
	"R15",
	"R16",
	"R17",
	"R18",
	"R19",
	"R20",
	"R21",
	"R22",
	"R23",
	"R24",
	"R25",
	"R26",
	"R27",
	"R28",
	"R29",
	"g",   // REGG.  Using name "g" and setting Config.hasGReg makes it "just happen".
	"R31", // REGTMP

	"F0",
	"F1",
	"F2",
	"F3",
	"F4",
	"F5",
	"F6",
	"F7",
	"F8",

//    Upper bytes are junk.
//  - *const instructions may use a constant larger than the instruction can encode.
//    In this case the assembler expands to multiple instructions and uses tmp
//    register (R27).
//  - All 32-bit Ops will zero the upper 32 bits of the destination register.

// Suffixes encode the bit width of various instructions.
// D (double word) = 64 bit
// W (word)        = 32 bit
// H (half word)   = 16 bit

	MOVW	R19, 76(R29)
	MOVW	R20, 80(R29)
	// R21 already saved
	// R22 already saved.
	MOVW	R22, 84(R29)
	// R23 is tmp register.
	MOVW	R24, 88(R29)
	MOVW	R25, 92(R29)
	// R26 is reserved by kernel.
	// R27 is reserved by kernel.
	MOVW	R28, 96(R29)
	// R29 is SP.
	// R30 is g.
	// R31 is LR, which was saved by the prologue.

	CALL	runtime·wbBufFlush(SB)

	MOVW	4(R29), R20
	MOVW	8(R29), R21

	&& s > 64 && s <= 16*64 && s%16 == 0
	&& !config.noDuffDevice && logLargeCopy(v, s) =>
	(DUFFCOPY [8 * (64 - s/16)] dst src mem)
// 8 is the number of bytes to encode:
//
// LDP.P   16(R16), (R26, R27)
// STP.P   (R26, R27), 16(R17)
//
// 64 is number of these blocks. See runtime/duff_arm64.s:duffcopy

// large move uses a loop
(Move [s] dst src mem)
	&& s%16 == 0 && (s > 16*64 || config.noDuffDevice)