//  - *const instructions may use a constant larger than the instruction can encode.
//    In this case the assembler expands to multiple instructions and uses tmp
//    register (R23).

// Suffixes encode the bit width of various instructions.
// W (word)      = 32 bit
// H (half word) = 16 bit
// HU            = 16 bit unsigned
// B (byte)      = 8 bit
// BU            = 8 bit unsigned

	}
	fmt.Fprintln(w, "\tRET")
}

func copyMIPS64x(w io.Writer) {
	fmt.Fprintln(w, "TEXT runtime·duffcopy(SB), NOSPLIT|NOFRAME, $0-0")
	for i := 0; i < 128; i++ {
		fmt.Fprintln(w, "\tMOVV\t(R1), R23")
		fmt.Fprintln(w, "\tADDV\t$8, R1")
		fmt.Fprintln(w, "\tMOVV\tR23, (R2)")
		fmt.Fprintln(w, "\tADDV\t$8, R2")
		fmt.Fprintln(w)
	}
	fmt.Fprintln(w, "\tRET")
}

func zeroRISCV64(w io.Writer) {

	STP	(R12, R13), 11*8(RSP)
	STP	(R14, R15), 13*8(RSP)
	// R16, R17 may be clobbered by linker trampoline
	// R18 is unused.
	STP	(R19, R20), 15*8(RSP)
	STP	(R21, R22), 17*8(RSP)
	STP	(R23, R24), 19*8(RSP)
	STP	(R25, R26), 21*8(RSP)
	// R27 is temp register.
	// R28 is g.
	// R29 is frame pointer (unused).
	// R30 is LR, which was saved by the prologue.
	// R31 is SP.

#define R_x030	R26
#define R_x040	R14
#define R_x050	R15
#define R_x060	R16
#define R_x070	R17
#define R_x080	R18
#define R_x090	R19
#define R_x0a0	R20
#define R_x0b0	R21
#define R_x0c0	R22
#define R_x0d0	R23
#define R_x0e0	R24
#define R_x0f0	R28
#define R_x100	R29
#define R_x110	R27


// V0-V7 are A-H
// V8-V23 are used for the message schedule
#define KI	V24
#define FUNC	V25
#define S0	V26

#define R_x030	R11
#define R_x040	R14
#define R_x050	R15
#define R_x060	R16
#define R_x070	R17
#define R_x080	R18
#define R_x090	R19
#define R_x0a0	R20
#define R_x0b0	R21
#define R_x0c0	R22
#define R_x0d0	R23
#define R_x0e0	R24
#define R_x0f0	R25
#define R_x100	R26
#define R_x110	R27


// V0-V7 are A-H
// V8-V23 are used for the message schedule
#define KI	V24
#define FUNC	V25
#define S0	V26

#define R_x030	R11
#define R_x040	R14
#define R_x050	R15
#define R_x060	R16
#define R_x070	R17
#define R_x080	R18
#define R_x090	R19
#define R_x0a0	R20
#define R_x0b0	R21
#define R_x0c0	R22
#define R_x0d0	R23
#define R_x0e0	R24
#define R_x0f0	R25
#define R_x100	R26
#define R_x110	R27


// V0-V7 are A-H
// V8-V23 are used for the message schedule
#define KI	V24
#define FUNC	V25
#define S0	V26

	&& !config.noDuffDevice && logLargeCopy(v, s)  =>
	(DUFFCOPY [16 * (128 - s/8)] dst src mem)
// 16 and 128 are magic constants.  16 is the number of bytes to encode:
//	MOVV	(R1), R23
//	ADDV	$8, R1
//	MOVV	R23, (R2)
//	ADDV	$8, R2
// and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy.

// large or unaligned move uses a loop
(Move [s] {t} dst src mem)

				// if(g->panic != nil && g->panic->argp == FP) g->panic->argp = bottom-of-frame
				//
				//	MOVD g_panic(g), R22
				//	CMP R22, $0
				//	BEQ end
				//	MOVD panic_argp(R22), R23
				//	ADD $(autosize+8), R1, R24
				//	CMP R23, R24
				//	BNE end
				//	ADD $8, R1, R25
				//	MOVD R25, panic_argp(R22)
				// end:
				//	NOP
				//
				// The NOP is needed to give the jumps somewhere to land.

	&& !config.noDuffDevice && logLargeCopy(v, s)  =>
	(DUFFCOPY [16 * (128 - s/8)] dst src mem)
// 16 and 128 are magic constants.  16 is the number of bytes to encode:
//	MOVV	(R1), R23
//	ADDV	$8, R1
//	MOVV	R23, (R2)
//	ADDV	$8, R2
// and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy.

// large or unaligned move uses a loop
(Move [s] {t} dst src mem)

	"R5",
	"R6",
	"R7",
	"R8",
	"R9",
	"R10",
	"R11", // REGCTXT for closures
	"R12",
	"R13", // REGTLS
	"R14",
	"R15",
	"R16",
	"R17",
	"R18",
	"R19",
	"R20",
	"R21",
	"R22",
	"R23",
	"R24",
	"R25",
	"R26",
	"R27",
	"R28",
	"R29",
	"g",   // REGG.  Using name "g" and setting Config.hasGReg makes it "just happen".
	"R31", // REGTMP

	"F0",
	"F1",
	"F2",
	"F3",
	"F4",