LSR:               "LSR",
	LSR_ZZ:            "LSR.ZZ",
	LSR_S_EQ:          "LSR.S.EQ",
	LSR_S_NE:          "LSR.S.NE",
	LSR_S_CS:          "LSR.S.CS",
	LSR_S_CC:          "LSR.S.CC",
	LSR_S_MI:          "LSR.S.MI",
	LSR_S_PL:          "LSR.S.PL",
	LSR_S_VS:          "LSR.S.VS",
	LSR_S_VC:          "LSR.S.VC",
	LSR_S_HI:          "LSR.S.HI",
	LSR_S_LS:          "LSR.S.LS",

	ADDW $1864, R25, R6           <=>    add w6, w25, #0x748

Optionally-shifted registers are written as <Rm>{<shift><amount>}.
The <shift> can be <<(lsl), >>(lsr), ->(asr), @>(ror).

Examples:

	ADD R19>>30, R10, R24     <=>    add x24, x10, x19, lsr #30
	ADDW R26->24, R21, R15    <=>    add w15, w21, w26, asr #24

Extended registers are written as <Rm>{.<extend>{<<<amount>}}.

	case sxtb:
		return "SXTB"

	case sxth:
		return "SXTH"

	case sxtw:
		return "SXTW"

	case sxtx:
		return "SXTX"

	case lsl:
		return "LSL"

	case lsr:
		return "LSR"

	case asr:
		return "ASR"

	case ror:
		return "ROR"
	}
	return ""
}

type RegExtshiftAmount struct {
	reg       Reg
	extShift  ExtShift
	amount    uint8

	RotateRight      Shift = 3 // right rotate
	RotateRightExt   Shift = 4 // right rotate through carry (Count will always be 1)
)

var shiftName = [...]string{
	"LSL", "LSR", "ASR", "ROR", "RRX",
}

func (s Shift) String() string {
	if s < 5 {
		return shiftName[s]
	}
	return fmt.Sprintf("Shift(%d)", int(s))
}

// A RegShift is a register shifted by a constant.

	{0xffe0fc00, 0x9ac02000, LSLV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
	// LSR <Wd>, <Wn>, <Wm>
	{0xffe0fc00, 0x1ac02400, LSR, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
	// LSRV <Wd>, <Wn>, <Wm>
	{0xffe0fc00, 0x1ac02400, LSRV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
	// LSR <Xd>, <Xn>, <Xm>
	{0xffe0fc00, 0x9ac02400, LSR, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
	// LSRV <Xd>, <Xn>, <Xm>

	LSLW $5, R7, R22                           // f6681b53
	LSL $57, R17, R2                           // 221a47d3
	LSRW R9, R3, R12                           // 6c24c91a
	LSR R10, R5, R2                            // a224ca9a
	LSRW $1, R3, R16                           // 707c0153
	LSR $12, R1, R20                           // 34fc4cd3
	MADDW R13, R23, R3, R10                    // 6a5c0d1b
	MADD R5, R23, R10, R4                      // 445d059b

			switch a.extShift {
			default:
				extshift = "." + a.extShift.String()

			case lsl:
				extshift = "<<"
				amount = fmt.Sprintf("%d", a.amount)
				return reg + extshift + amount

			case lsr:
				extshift = ">>"
				amount = fmt.Sprintf("%d", a.amount)
				return reg + extshift + amount

			case asr:
				extshift = "->"
				amount = fmt.Sprintf("%d", a.amount)
				return reg + extshift + amount

	// s390x:-"STMG",-"MOVD"
	p[1] = y
}

func store32le(p *struct{ a, b uint32 }, x uint64) {
	// amd64:"MOVQ",-"MOVL",-"SHRQ"
	// arm64:"MOVD",-"MOVW",-"LSR"
	// ppc64le:"MOVD",-"MOVW",-"SRD"
	p.a = uint32(x)
	// amd64:-"MOVL",-"SHRQ"
	// arm64:-"MOVW",-"LSR"
	// ppc64le:-"MOVW",-"SRD"
	p.b = uint32(x >> 32)
}
func store32be(p *struct{ a, b uint32 }, x uint64) {
	// ppc64:"MOVD",-"MOVW",-"SRD"

	// amd64:"ROLW" 386:"ROLW"
	// arm64:"RORW",-"CSEL"
	return bits.RotateLeft16(n, s)
}

func RotateLeft8(n uint8, s int) uint8 {
	// amd64:"ROLB" 386:"ROLB"
	// arm64:"LSL","LSR",-"CSEL"
	return bits.RotateLeft8(n, s)
}

func RotateLeftVariable(n uint, m int) uint {
	// amd64:"ROLQ"
	// arm64:"ROR"
	// ppc64x:"ROTL"
	// s390x:"RLLG"
	// wasm:"I64Rotl"

{"Name":"LSR (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSR <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the LSRV instruction."},