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Results 31 - 40 of 46 for r28 (0.1 sec)
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src/runtime/signal_linux_mipsx.go
func (c *sigctxt) r26() uint32 { return uint32(c.regs().sc_regs[26]) } func (c *sigctxt) r27() uint32 { return uint32(c.regs().sc_regs[27]) } func (c *sigctxt) r28() uint32 { return uint32(c.regs().sc_regs[28]) } func (c *sigctxt) r29() uint32 { return uint32(c.regs().sc_regs[29]) } func (c *sigctxt) r30() uint32 { return uint32(c.regs().sc_regs[30]) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 28 18:17:57 UTC 2021 - 3.7K bytes - Viewed (0) -
src/crypto/md5/md5block_ppc64x.s
MOVD $off,idx; \ MOVWBR (idx)(ptr), dst #endif #define M00 R18 #define M01 R19 #define M02 R20 #define M03 R24 #define M04 R25 #define M05 R26 #define M06 R27 #define M07 R28 #define M08 R29 #define M09 R21 #define M10 R11 #define M11 R8 #define M12 R7 #define M13 R12 #define M14 R23 #define M15 R10 #define ROUND1(a, b, c, d, index, const, shift) \ ADD $const, index, R9; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 20 18:05:32 UTC 2024 - 5.3K bytes - Viewed (0) -
src/runtime/race_arm64.s
// A brief recap of the arm64 calling convention. // Arguments are passed in R0...R7, the rest is on stack. // Callee-saved registers are: R19...R28. // Temporary registers are: R9...R15 // SP must be 16-byte aligned. // When calling racecalladdr, R9 is the call target address. // The race ctx, ThreadState *thr below, is passed in R0 and loaded in racecalladdr.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 18:37:29 UTC 2024 - 15.5K bytes - Viewed (0) -
src/runtime/asm_ppc64x.s
MOVD R19, 200(R1) MOVD R20, 208(R1) MOVD R21, 216(R1) MOVD R22, 224(R1) MOVD R23, 232(R1) MOVD R24, 240(R1) MOVD R25, 248(R1) MOVD R26, 256(R1) MOVD R27, 264(R1) MOVD R28, 272(R1) MOVD R29, 280(R1) MOVD g, 288(R1) MOVD LR, R31 MOVD R31, 32(R1) CALL runtime·debugCallCheck(SB) MOVD 40(R1), R22 XOR R0, R0 CMP R22, $0 BEQ good MOVD 48(R1), R22
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 45.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
"R11", "R12", "R13", "R14", "R15", "R16", "R17", "R18", "R19", "R20", "R21", "R22", //REGTMP "R24", "R25", // R26 reserved by kernel // R27 reserved by kernel "R28", "SP", // aka R29 "g", // aka R30 "R31", // REGLINK // odd FP registers contain high parts of 64-bit FP values "F0", "F2", "F4", "F6", "F8", "F10", "F12", "F14", "F16",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/runtime/asm_loong64.s
// R22 is g. MOVV R23, 160(R3) MOVV R24, 168(R3) MOVV R25, 176(R3) MOVV R26, 184(R3) // R27 already saved // R28 already saved. MOVV R29, 192(R3) // R30 is tmp register. MOVV R31, 200(R3) CALL runtime·wbBufFlush(SB) MOVV 8(R3), R27 MOVV 16(R3), R28 MOVV 24(R3), R2 MOVV 32(R3), R4 MOVV 40(R3), R5 MOVV 48(R3), R6 MOVV 56(R3), R7 MOVV 64(R3), R8 MOVV 72(R3), R9
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 13 15:04:25 UTC 2024 - 26.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0) -
src/crypto/sha512/sha512block_ppc64x.s
#define R_x050 R15 #define R_x060 R16 #define R_x070 R17 #define R_x080 R18 #define R_x090 R19 #define R_x0a0 R20 #define R_x0b0 R21 #define R_x0c0 R22 #define R_x0d0 R23 #define R_x0e0 R24 #define R_x0f0 R28 #define R_x100 R29 #define R_x110 R27 // V0-V7 are A-H // V8-V23 are used for the message schedule #define KI V24 #define FUNC V25 #define S0 V26 #define S1 V27 #define s0 V28 #define s1 V29
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 15.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/runtime/asm_mipsx.s
// R21 already saved // R22 already saved. MOVW R22, 84(R29) // R23 is tmp register. MOVW R24, 88(R29) MOVW R25, 92(R29) // R26 is reserved by kernel. // R27 is reserved by kernel. MOVW R28, 96(R29) // R29 is SP. // R30 is g. // R31 is LR, which was saved by the prologue. CALL runtime·wbBufFlush(SB) MOVW 4(R29), R20 MOVW 8(R29), R21 MOVW 12(R29), R3 MOVW 16(R29), R4
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 11:46:29 UTC 2024 - 26.3K bytes - Viewed (0)