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src/cmd/internal/notsha256/sha256block_ppc64x.s
#define R_x070 R17 #define R_x080 R18 #define R_x090 R19 #define R_x0a0 R20 #define R_x0b0 R21 #define R_x0c0 R22 #define R_x0d0 R23 #define R_x0e0 R24 #define R_x0f0 R25 #define R_x100 R26 #define R_x110 R27 // V0-V7 are A-H // V8-V23 are used for the message schedule #define KI V24 #define FUNC V25 #define S0 V26 #define S1 V27 #define s0 V28 #define s1 V29
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 14.5K bytes - Viewed (0) -
src/internal/bytealg/index_ppc64x.s
// R17=index value 17 // R18=index value 18 // R19=index value 1 // R26=LASTBYTE of string // R27=LASTSTR last start byte to compare with sep // R8, R9 scratch // V0=sep left justified zero fill // CR4=sep length >= 16 #define SEPMASK V17 #define LASTBYTE R26 #define LASTSTR R27 #define ONES V20 #define SWAP V21 #define SWAP_ VS53 TEXT indexbody<>(SB), NOSPLIT|NOFRAME, $0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 31.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
"R9", "R10", "R11", "R12", "R13", "R14", "R15", "R16", "R17", "R18", "R19", "R20", "R21", "R22", //REGTMP "R24", "R25", // R26 reserved by kernel // R27 reserved by kernel "R28", "SP", // aka R29 "g", // aka R30 "R31", // REGLINK // odd FP registers contain high parts of 64-bit FP values "F0", "F2", "F4", "F6", "F8", "F10", "F12",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
"R10", "R11", // REGCTXT for closures "R12", "R13", // REGTLS "R14", "R15", "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", "R24", "R25", "R26", "R27", "R28", "R29", "g", // REGG. Using name "g" and setting Config.hasGReg makes it "just happen". "R31", // REGTMP "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", "F8",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
"R11", "R12", "R13", "R14", "R15", "R16", "R17", "R18", "R19", "R20", "R21", "R22", // R23 = REGTMP not used in regalloc "R24", "R25", // R26 reserved by kernel // R27 reserved by kernel // R28 = REGSB not used in regalloc "SP", // aka R29 "g", // aka R30 "R31", // aka REGLINK "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", "F8", "F9",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/runtime/asm_mips64x.s
MOVV R19, 152(R29) // R20 already saved // R21 already saved. MOVV R22, 160(R29) // R23 is tmp register. MOVV R24, 168(R29) MOVV R25, 176(R29) // R26 is reserved by kernel. // R27 is reserved by kernel. // R28 is REGSB (not modified by Go code). // R29 is SP. // R30 is g. // R31 is LR, which was saved by the prologue. CALL runtime·wbBufFlush(SB) MOVV 8(R29), R20
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 06 19:45:59 UTC 2023 - 24.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
// Upper bytes are junk. // - *const instructions may use a constant larger than the instruction can encode. // In this case the assembler expands to multiple instructions and uses tmp // register (R27). // - All 32-bit Ops will zero the upper 32 bits of the destination register. // Suffixes encode the bit width of various instructions. // D (double word) = 64 bit // W (word) = 32 bit // H (half word) = 16 bit
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/runtime/asm_mipsx.s
MOVW R19, 76(R29) MOVW R20, 80(R29) // R21 already saved // R22 already saved. MOVW R22, 84(R29) // R23 is tmp register. MOVW R24, 88(R29) MOVW R25, 92(R29) // R26 is reserved by kernel. // R27 is reserved by kernel. MOVW R28, 96(R29) // R29 is SP. // R30 is g. // R31 is LR, which was saved by the prologue. CALL runtime·wbBufFlush(SB) MOVW 4(R29), R20 MOVW 8(R29), R21
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 11:46:29 UTC 2024 - 26.3K bytes - Viewed (0) -
doc/asm.html
</li> </ul> <h3 id="arm64">ARM64</h3> <p> <code>R18</code> is the "platform register", reserved on the Apple platform. To prevent accidental misuse, the register is named <code>R18_PLATFORM</code>. <code>R27</code> and <code>R28</code> are reserved by the compiler and linker. <code>R29</code> is the frame pointer. <code>R30</code> is the link register. </p> <p>
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
&& s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) => (DUFFCOPY [8 * (64 - s/16)] dst src mem) // 8 is the number of bytes to encode: // // LDP.P 16(R16), (R26, R27) // STP.P (R26, R27), 16(R17) // // 64 is number of these blocks. See runtime/duff_arm64.s:duffcopy // large move uses a loop (Move [s] dst src mem) && s%16 == 0 && (s > 16*64 || config.noDuffDevice)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0)