// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
		// and sorts it to the very beginning of the block to prevent other
		// use of R22 (mips.REGCTXT, the closure pointer)
		{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("R22")}}, zeroWidth: true},

		// LoweredGetCallerSP returns the SP of the caller of the current function. arg0=mem.

	LDP	1*16(a_ptr), (R6, R7)
	LDP	2*16(a_ptr), (R8, R9)
	LDP	0*16(b_ptr), (R16, R17)
	LDP	1*16(b_ptr), (R19, R20)
	LDP	2*16(b_ptr), (R21, R22)
	CSEL	EQ, R16, R4, R4
	CSEL	EQ, R17, R5, R5
	CSEL	EQ, R19, R6, R6
	CSEL	EQ, R20, R7, R7
	CSEL	EQ, R21, R8, R8
	CSEL	EQ, R22, R9, R9
	STP	(R4, R5), 0*16(res_ptr)
	STP	(R6, R7), 1*16(res_ptr)
	STP	(R8, R9), 2*16(res_ptr)

	LDP	3*16(a_ptr), (R4, R5)

				// if(g->panic != nil && g->panic->argp == FP) g->panic->argp = bottom-of-frame
				//
				//	MOVD g_panic(g), R22
				//	CMP R22, $0
				//	BEQ end
				//	MOVD panic_argp(R22), R23
				//	ADD $(autosize+8), R1, R24
				//	CMP R23, R24
				//	BNE end
				//	ADD $8, R1, R25
				//	MOVD R25, panic_argp(R22)
				// end:
				//	NOP
				//
				// The NOP is needed to give the jumps somewhere to land.

	MOVD $48, R18; \
	MOVD $64, R19; \
	MOVD $80, R20; \
	MOVD $96, R21; \
	MOVD $112, R22; \
	P8_LXVB16X(blk_inp,R0,V1); \
	P8_LXVB16X(blk_inp,R16,V2); \
	P8_LXVB16X(blk_inp,R17,V3); \
	P8_LXVB16X(blk_inp,R18,V4); \
	P8_LXVB16X(blk_inp,R19,V5); \
	P8_LXVB16X(blk_inp,R20,V6); \
	P8_LXVB16X(blk_inp,R21,V7); \
	P8_LXVB16X(blk_inp,R22,V8); \
	ADD $128, blk_inp

// Finish encryption on 8 streams and

	MOVW	R13, 52(R29)
	MOVW	R14, 56(R29)
	MOVW	R15, 60(R29)
	MOVW	R16, 64(R29)
	MOVW	R17, 68(R29)
	MOVW	R18, 72(R29)
	MOVW	R19, 76(R29)
	MOVW	R20, 80(R29)
	// R21 already saved
	// R22 already saved.
	MOVW	R22, 84(R29)
	// R23 is tmp register.
	MOVW	R24, 88(R29)
	MOVW	R25, 92(R29)
	// R26 is reserved by kernel.
	// R27 is reserved by kernel.
	MOVW	R28, 96(R29)
	// R29 is SP.
	// R30 is g.

	"SP", // aka R3
	"R4",
	"R5",
	"R6",
	"R7",
	"R8",
	"R9",
	"R10",
	"R11",
	"R12",
	"R13",
	"R14",
	"R15",
	"R16",
	"R17",
	"R18",
	"R19",
	"R20",
	"R21",
	"g", // aka R22
	"R23",
	"R24",
	"R25",
	"R26",
	"R27",
	"R28",
	"R29",
	// R30 is REGTMP not used in regalloc
	"R31",

	"F0",
	"F1",
	"F2",
	"F3",
	"F4",
	"F5",
	"F6",
	"F7",
	"F8",

// license that can be found in the LICENSE file.

//go:build mips64 || mips64le

#include "go_asm.h"
#include "go_tls.h"
#include "funcdata.h"
#include "textflag.h"

#define	REGCTXT	R22

TEXT runtime·rt0_go(SB),NOSPLIT|TOPFRAME,$0
	// R29 = stack; R4 = argc; R5 = argv

	ADDV	$-24, R29
	MOVW	R4, 8(R29) // argc
	MOVV	R5, 16(R29) // argv

	if _64bit {
		mov = "MOVV"
		movf = "MOVD"
		add = "ADDV"
		sub = "SUBV"
		r28 = "RSB"
		regsize = 8
		softfloat = "GOMIPS64_softfloat"
	}

	// Add integer registers R1-R22, R24-R25, R28
	// R0 (zero), R23 (REGTMP), R29 (SP), R30 (g), R31 (LR) are special,
	// and not saved here. R26 and R27 are reserved by kernel and not used.

	MOVW	machTimebaseInfo_denom(RSP), R21
	ADD	$(machTimebaseInfo__size+15)/16*16, RSP

	MOVW	R20, timebase<>+machTimebaseInfo_numer(SB)
	MOVD	$timebase<>+machTimebaseInfo_denom(SB), R22
	STLRW	R21, (R22)	// atomic write

initialized:
	MOVW	R20, 8(R19)
	MOVW	R21, 12(R19)
	RET

TEXT runtime·sigfwd(SB),NOSPLIT,$0-32
	MOVW	sig+8(FP), R0
	MOVD	info+16(FP), R1
	MOVD	ctx+24(FP), R2

		register[obj.Rconv(i)] = int16(i)
	}
	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC
	// Avoid unintentionally clobbering g using R22.
	delete(register, "R22")
	register["g"] = loong64.REG_R22
	registerPrefix := map[string]bool{
		"F":    true,
		"FCSR": true,
		"FCC":  true,
		"R":    true,
	}

	instructions := make(map[string]obj.As)