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Results 1 - 10 of 18 for vrlw (0.13 sec)

  1. src/vendor/golang.org/x/crypto/chacha20/chacha_ppc64le.s

    	VADDUWM V8, V12, V8
    	VADDUWM V9, V13, V9
    	VADDUWM V10, V14, V10
    	VADDUWM V11, V15, V11
    
    	VXOR V4, V8, V4
    	VXOR V5, V9, V5
    	VXOR V6, V10, V6
    	VXOR V7, V11, V7
    
    	VRLW V4, V28, V4
    	VRLW V5, V28, V5
    	VRLW V6, V28, V6
    	VRLW V7, V28, V7
    
    	VADDUWM V0, V4, V0
    	VADDUWM V1, V5, V1
    	VADDUWM V2, V6, V2
    	VADDUWM V3, V7, V3
    
    	VPERMXOR V12, V0, V20, V12
    	VPERMXOR V13, V1, V20, V13
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 05 22:18:42 UTC 2024
    - 9K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/ppc64/anames.go

    	"VMULOSW",
    	"VMULEUW",
    	"VMULOUW",
    	"VMULUWM",
    	"VPMSUM",
    	"VPMSUMB",
    	"VPMSUMH",
    	"VPMSUMW",
    	"VPMSUMD",
    	"VMSUMUDM",
    	"VR",
    	"VRLB",
    	"VRLH",
    	"VRLW",
    	"VRLD",
    	"VS",
    	"VSLB",
    	"VSLH",
    	"VSLW",
    	"VSL",
    	"VSLO",
    	"VSRB",
    	"VSRH",
    	"VSRW",
    	"VSR",
    	"VSRO",
    	"VSLD",
    	"VSRD",
    	"VSA",
    	"VSRAB",
    	"VSRAH",
    	"VSRAW",
    	"VSRAD",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/ppc64.s

    	VMSUMUDM V1, V2, V3, V4         // 108110e3
    	VRLB V1, V2, V3                 // 10611004
    	VRLH V1, V2, V3                 // 10611044
    	VRLW V1, V2, V3                 // 10611084
    	VRLD V1, V2, V3                 // 106110c4
    	VSLB V1, V2, V3                 // 10611104
    	VSLH V1, V2, V3                 // 10611144
    	VSLW V1, V2, V3                 // 10611184
    	VSL V1, V2, V3                  // 106111c4
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  4. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

    	VRFIP:          "vrfip",
    	VRFIZ:          "vrfiz",
    	VRLB:           "vrlb",
    	VRLH:           "vrlh",
    	VRLW:           "vrlw",
    	VRSQRTEFP:      "vrsqrtefp",
    	VSEL:           "vsel",
    	VSL:            "vsl",
    	VSLB:           "vslb",
    	VSLDOI:         "vsldoi",
    	VSLH:           "vslh",
    	VSLO:           "vslo",
    	VSLW:           "vslw",
    	VSPLTB:         "vspltb",
    	VSPLTH:         "vsplth",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 334.7K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/ppc64/asm9.go

    		case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */
    			opset(AVPMSUMB, r0)
    			opset(AVPMSUMH, r0)
    			opset(AVPMSUMW, r0)
    			opset(AVPMSUMD, r0)
    
    		case AVR: /* vrlb, vrlh, vrlw, vrld */
    			opset(AVRLB, r0)
    			opset(AVRLH, r0)
    			opset(AVRLW, r0)
    			opset(AVRLD, r0)
    
    		case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */
    			opset(AVSLB, r0)
    			opset(AVSLH, r0)
    			opset(AVSLW, r0)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 13:55:28 UTC 2024
    - 156.1K bytes
    - Viewed (0)
  6. tests/testdata/certs/ca.crl

    adVfSZj8c+W+z97znx51Zn4cZQpxlD28KRgJ9YWo7zPLRpiq1SoRi9tDxr8gmcnp
    7+nAY00nblnQw/iiguLPAyqpmPLidn05EpjawTLMYVeaSGKtr1kjtj3dCVl3HOTS
    +iFR/xq3kMAhx7aPTRJlmKYntMazJMxB6r3h0ho3hsH7AUPcWkc70jRJhQkG0tMP
    VnLW
    Registered: Fri Jun 14 15:00:06 UTC 2024
    - Last Modified: Wed Jul 05 19:49:21 UTC 2023
    - 638 bytes
    - Viewed (0)
  7. src/cmd/internal/obj/riscv/anames.go

    	"BGEU",
    	"LW",
    	"LWU",
    	"LH",
    	"LHU",
    	"LB",
    	"LBU",
    	"SW",
    	"SH",
    	"SB",
    	"FENCE",
    	"FENCETSO",
    	"PAUSE",
    	"ADDIW",
    	"SLLIW",
    	"SRLIW",
    	"SRAIW",
    	"ADDW",
    	"SLLW",
    	"SRLW",
    	"SUBW",
    	"SRAW",
    	"LD",
    	"SD",
    	"MUL",
    	"MULH",
    	"MULHU",
    	"MULHSU",
    	"MULW",
    	"DIV",
    	"DIVU",
    	"REM",
    	"REMU",
    	"DIVW",
    	"DIVUW",
    	"REMW",
    	"REMUW",
    	"LRD",
    	"SCD",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Rsh32Ux8  <t> x y) && !shiftIsBounded(v) => (AND (SRLW <t>  x                y) (Neg32 <t> (SLTIU <t> [32] (ZeroExt8to64  y))))
    (Rsh32Ux16 <t> x y) && !shiftIsBounded(v) => (AND (SRLW <t>  x                y) (Neg32 <t> (SLTIU <t> [32] (ZeroExt16to64 y))))
    (Rsh32Ux32 <t> x y) && !shiftIsBounded(v) => (AND (SRLW <t>  x                y) (Neg32 <t> (SLTIU <t> [32] (ZeroExt32to64 y))))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/testdata/riscv64.s

    	ADDW	X5, X6, X7				// bb035300
    	SLLW	X5, X6, X7				// bb135300
    	SRLW	X5, X6, X7				// bb535300
    	SUBW	X5, X6, X7				// bb035340
    	SRAW	X5, X6, X7				// bb535340
    	ADDIW	$1, X6					// 1b031300
    	SLLIW	$1, X6					// 1b131300
    	SRLIW	$1, X6					// 1b531300
    	SRAIW	$1, X6					// 1b531340
    	ADDW	X5, X7					// bb835300
    	SLLW	X5, X7					// bb935300
    	SRLW	X5, X7					// bbd35300
    	SUBW	X5, X7					// bb835340
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/rewrite.go

    func mergePPC64MovwzregRlwinm(rlw int64) int64 {
    	_, mb, me, _ := DecodePPC64RotateMask(rlw)
    	if mb > me {
    		return 0
    	}
    	return rlw
    }
    
    // Test if AND feeding into an ANDconst can be merged. Return the encoded RLWINM constant,
    // or 0 if they cannot be merged.
    func mergePPC64RlwinmAnd(rlw int64, mask uint32) int64 {
    	r, _, _, mask_rlw := DecodePPC64RotateMask(rlw)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 64.2K bytes
    - Viewed (0)
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