BGE    CR4, loadge16       // Load for len(sep) >= 16
	SUB    R6, R16, R9         // 16-len of sep
	SLD    $3, R9              // Set up for VSLO
	MTVSRD R9, V9              // Set up for VSLO
	VSLDOI $8, V9, V9, V9      // Set up for VSLO
	VSLO   ONES, V9, SEPMASK   // Mask for separator len(sep) < 16

loadge16:
	ANDCC $15, R5, R9 // Find byte offset of sep
	ADD   R9, R6, R10 // Add sep len

	"VPMSUMB",
	"VPMSUMH",
	"VPMSUMW",
	"VPMSUMD",
	"VMSUMUDM",
	"VR",
	"VRLB",
	"VRLH",
	"VRLW",
	"VRLD",
	"VS",
	"VSLB",
	"VSLH",
	"VSLW",
	"VSL",
	"VSLO",
	"VSRB",
	"VSRH",
	"VSRW",
	"VSR",
	"VSRO",
	"VSLD",
	"VSRD",
	"VSA",
	"VSRAB",
	"VSRAH",
	"VSRAW",
	"VSRAD",
	"VSOI",
	"VSLDOI",
	"VCLZ",
	"VCLZB",
	"VCLZH",
	"VCLZW",

	VRLW V1, V2, V3                 // 10611084
	VRLD V1, V2, V3                 // 106110c4
	VSLB V1, V2, V3                 // 10611104
	VSLH V1, V2, V3                 // 10611144
	VSLW V1, V2, V3                 // 10611184
	VSL V1, V2, V3                  // 106111c4
	VSLO V1, V2, V3                 // 1061140c
	VSRB V1, V2, V3                 // 10611204
	VSRH V1, V2, V3                 // 10611244

	VRLB:           "vrlb",
	VRLH:           "vrlh",
	VRLW:           "vrlw",
	VRSQRTEFP:      "vrsqrtefp",
	VSEL:           "vsel",
	VSL:            "vsl",
	VSLB:           "vslb",
	VSLDOI:         "vsldoi",
	VSLH:           "vslh",
	VSLO:           "vslo",
	VSLW:           "vslw",
	VSPLTB:         "vspltb",
	VSPLTH:         "vsplth",
	VSPLTISB:       "vspltisb",
	VSPLTISH:       "vspltish",

//CHECK-SAME: padding = #vhlo.tensor_v1<dense<0> : tensor<2x2xi64>>,
//CHECK-SAME: precision_config = #vhlo.array_v1<[#vhlo<precision_v1 DEFAULT>, #vhlo<precision_v1 DEFAULT>]>,
//CHECK-SAME: rhs_dilation = #vhlo.tensor_v1<dense<1> : tensor<2xi64>>,
//CHECK-SAME: window_reversal = #vhlo.tensor_v1<dense<false> : tensor<2xi1>>,

// RUN: odml-to-stablehlo-opt %s --stablehlo-legalize-vhlo -split-input-file | FileCheck %s
// RUN: odml-to-stablehlo-opt --stablehlo-legalize-vhlo %s | odml-to-stablehlo-opt --vhlo-legalize-stablehlo > %t.0
// RUN: odml-to-stablehlo-opt %s > %t.1
// RUN: diff %t.0 %t.1

// CHECK-LABEL: op_tfl
func.func @op_tfl(%arg0 : tensor<f32>) -> (tensor<f32>) {
  // CHECK: %0 = tfl.add %arg0, %arg0 {fused_activation_function = "NONE"} : tensor<f32>

    else if (llvm::isa<mlir::vhlo::BooleanV1Attr>(attr))
      flex_builder->Bool(name.c_str(),
                         attr.cast<mlir::vhlo::BooleanV1Attr>().getValue());
    else if (llvm::isa<mlir::vhlo::StringV1Attr>(attr))
      flex_builder->String(
          name.c_str(), attr.cast<mlir::vhlo::StringV1Attr>().getValue().str());
    else if (llvm::isa<mlir::vhlo::IntegerV1Attr>(attr))
      flex_builder->Int(

	"VPDI",
	"VPOPCT",
	"VREP",
	"VREPB",
	"VREPH",
	"VREPF",
	"VREPG",
	"VREPI",
	"VREPIB",
	"VREPIH",
	"VREPIF",
	"VREPIG",
	"VSCEF",
	"VSCEG",
	"VSEL",
	"VSL",
	"VSLB",
	"VSLDB",
	"VSRA",
	"VSRAB",
	"VSRL",
	"VSRLB",
	"VSEG",
	"VSEGB",
	"VSEGH",
	"VSEGF",
	"VST",
	"VSTEH",
	"VSTEF",
	"VSTEG",
	"VSTEB",
	"VSTM",
	"VSTL",

//CHECK-SAME: backend_config = #vhlo.string_v1<"">,
//CHECK-SAME: call_target_name = #vhlo.string_v1<"tf.ResizeBilinear">,
//CHECK-SAME: called_computations = #vhlo.array_v1<[]>,
//CHECK-SAME: has_side_effect = #vhlo.bool_v1<false>,
//CHECK-SAME: operand_layouts = #vhlo.array_v1<[]>,
//CHECK-SAME: output_operand_aliases = #vhlo.array_v1<[]>,

  void runOnOperation() override {
    // Revert the tensor types to VHLO
    auto module = getOperation();
    StablehloToOdmlTypeConverter to_vhlo_converter;

    // Builtin Tensor --> VHLO Tensor
    //   StableHLO --> VHLO
    //     VHLO --> Upgrade to current
    //       VHLO --> StableHLO
    //         Remove cast(tensor->vhlo) -> cast(vhlo->tensor) pattern
    if (failed(ApplyTypeConverter(module, to_vhlo_converter)) ||