"VMULUWM",
	"VPMSUM",
	"VPMSUMB",
	"VPMSUMH",
	"VPMSUMW",
	"VPMSUMD",
	"VMSUMUDM",
	"VR",
	"VRLB",
	"VRLH",
	"VRLW",
	"VRLD",
	"VS",
	"VSLB",
	"VSLH",
	"VSLW",
	"VSL",
	"VSLO",
	"VSRB",
	"VSRH",
	"VSRW",
	"VSR",
	"VSRO",
	"VSLD",
	"VSRD",
	"VSA",
	"VSRAB",
	"VSRAH",
	"VSRAW",
	"VSRAD",
	"VSOI",
	"VSLDOI",
	"VCLZ",

	"VREP",
	"VREPB",
	"VREPH",
	"VREPF",
	"VREPG",
	"VREPI",
	"VREPIB",
	"VREPIH",
	"VREPIF",
	"VREPIG",
	"VSCEF",
	"VSCEG",
	"VSEL",
	"VSL",
	"VSLB",
	"VSLDB",
	"VSRA",
	"VSRAB",
	"VSRL",
	"VSRLB",
	"VSEG",
	"VSEGB",
	"VSEGH",
	"VSEGF",
	"VST",
	"VSTEH",
	"VSTEF",
	"VSTEG",
	"VSTEB",
	"VSTM",
	"VSTL",
	"VSTRC",
	"VSTRCB",

	VESLG $26, H_1, H_1
	VESLG $26, H_3, H_3
	VO    H_0, H_1, H_0
	VO    H_2, H_3, H_2
	VESLG $4, H_2, H_2
	VLEIB $7, $48, H_1
	VSLB  H_1, H_2, H_2
	VO    H_0, H_2, H_0
	VLEIB $7, $104, H_1
	VSLB  H_1, H_4, H_3
	VO    H_3, H_0, H_0
	VLEIB $7, $24, H_1
	VSRLB H_1, H_4, H_1

	// update state
	VSTEG $1, H_0, 0(R1)
	VSTEG $0, H_0, 8(R1)
	VSTEG $1, H_1, 16(R1)
	RET

	VMSUMUDM V1, V2, V3, V4         // 108110e3
	VRLB V1, V2, V3                 // 10611004
	VRLH V1, V2, V3                 // 10611044
	VRLW V1, V2, V3                 // 10611084
	VRLD V1, V2, V3                 // 106110c4
	VSLB V1, V2, V3                 // 10611104
	VSLH V1, V2, V3                 // 10611144
	VSLW V1, V2, V3                 // 10611184
	VSL V1, V2, V3                  // 106111c4

	VRFIP:          "vrfip",
	VRFIZ:          "vrfiz",
	VRLB:           "vrlb",
	VRLH:           "vrlh",
	VRLW:           "vrlw",
	VRSQRTEFP:      "vrsqrtefp",
	VSEL:           "vsel",
	VSL:            "vsl",
	VSLB:           "vslb",
	VSLDOI:         "vsldoi",
	VSLH:           "vslh",
	VSLO:           "vslo",
	VSLW:           "vslw",
	VSPLTB:         "vspltb",
	VSPLTH:         "vsplth",

	"VMOVD",
	"VMOVI",
	"VMOVQ",
	"VMOVS",
	"VORR",
	"VPMULL",
	"VPMULL2",
	"VRAX1",
	"VRBIT",
	"VREV16",
	"VREV32",
	"VREV64",
	"VSHL",
	"VSLI",
	"VSRI",
	"VST1",
	"VST2",
	"VST3",
	"VST4",
	"VSUB",
	"VTBL",
	"VTBX",
	"VTRN1",
	"VTRN2",
	"VUADDLV",
	"VUADDW",
	"VUADDW2",
	"VUMAX",
	"VUMIN",
	"VUSHLL",
	"VUSHLL2",
	"VUSHR",
	"VUSRA",

        ]
    )
    fun branchesWithVcsTriggerEnabled(branchName: String, expectedNightlyPromotionTriggerHour: Int?) {
        val vsb = VersionedSettingsBranch(branchName)
        assertTrue(vsb.enableVcsTriggers)
        assertEquals(expectedNightlyPromotionTriggerHour, vsb.nightlyPromotionTriggerHour)
    }

    @ParameterizedTest
    @ValueSource(
        strings = [
            "experimental",

	BGE    CR4, loadge16       // Load for len(sep) >= 16
	SUB    R6, R16, R9         // 16-len of sep
	SLD    $3, R9              // Set up for VSLO
	MTVSRD R9, V9              // Set up for VSLO
	VSLDOI $8, V9, V9, V9      // Set up for VSLO
	VSLO   ONES, V9, SEPMASK   // Mask for separator len(sep) < 16

loadge16:
	ANDCC $15, R5, R9 // Find byte offset of sep
	ADD   R9, R6, R10 // Add sep len

	VSLDB $8, T1, T0, T0
	VSLDB $8, T2, T1, T1

	VACCQ  T0, RED1, CAR1
	VAQ    T0, RED1, T0
	VACCCQ T1, RED2, CAR1, CAR2
	VACQ   T1, RED2, CAR1, T1
	VAQ    T2, CAR2, T2

	// Last round
	VPERM T1, T0, SEL1, RED2    // d1 d0 d1 d0
	VPERM ZER, RED2, SEL2, RED1 // 0  d1 d0  0
	VSQ   RED1, RED2, RED2      // Guaranteed not to underflow

	VSLDB $8, T1, T0, T0
	VSLDB $8, T2, T1, T1

	VPGATHERDD Y5, -8(X14*8), Y6    // ERROR "invalid instruction"
	// No VSIB for legacy instructions.
	MOVL (AX)(X0*1), AX             // ERROR "invalid instruction"
	MOVL (AX)(Y0*1), AX             // ERROR "invalid instruction"
	// VSIB/VM is invalid without vector index.
	// TODO(quasilyte): improve error message (#21860).
	// "invalid VSIB address (missing vector index)"
	VPGATHERQQ Y2, (BP), Y1         // ERROR "invalid instruction"