Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 10 of 40 for vdivsd (0.23 sec)

  1. src/cmd/asm/internal/asm/testdata/ppc64_p10.s

    	VCTZDM V1, V2, V3                       // 106117c4
    	VDIVESD V1, V2, V3                      // 106113cb
    	VDIVESQ V1, V2, V3                      // 1061130b
    	VDIVESW V1, V2, V3                      // 1061138b
    	VDIVEUD V1, V2, V3                      // 106112cb
    	VDIVEUQ V1, V2, V3                      // 1061120b
    	VDIVEUW V1, V2, V3                      // 1061128b
    	VDIVSD V1, V2, V3                       // 106111cb
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 23 20:52:57 UTC 2023
    - 14.3K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/x86/anames.go

    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 19.1K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/ppc64/asm9_gtables.go

    	"VEXTDUBVLX",
    	"VEXTDDVRX",
    	"VEXTDDVLX",
    	"VEXPANDWM",
    	"VEXPANDQM",
    	"VEXPANDHM",
    	"VEXPANDDM",
    	"VEXPANDBM",
    	"VDIVUW",
    	"VDIVUQ",
    	"VDIVUD",
    	"VDIVSW",
    	"VDIVSQ",
    	"VDIVSD",
    	"VDIVEUW",
    	"VDIVEUQ",
    	"VDIVEUD",
    	"VDIVESW",
    	"VDIVESQ",
    	"VDIVESD",
    	"VCTZDM",
    	"VCNTMBW",
    	"VCNTMBH",
    	"VCNTMBD",
    	"VCNTMBB",
    	"VCMPUQ",
    	"VCMPSQ",
    	"VCMPGTUQCC",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 16 20:18:50 UTC 2022
    - 42.6K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/avx512enc/avx512f.s

    	VDIVPD Z16, Z21, K3, Z14                           // 6231d5435ef0
    	VDIVPD Z9, Z21, K3, Z14                            // 6251d5435ef1
    	VDIVPD Z16, Z8, K3, Z14                            // 6231bd4b5ef0
    	VDIVPD Z9, Z8, K3, Z14                             // 6251bd4b5ef1
    	VDIVPD Z16, Z21, K3, Z15                           // 6231d5435ef8
    	VDIVPD Z9, Z21, K3, Z15                            // 6251d5435ef9
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 410.5K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/amd64enc.s

    	VDIVPS (R11), Y15, Y11                  // c441045e1b
    	VDIVPS Y2, Y15, Y11                     // c461045eda or c5045eda
    	VDIVPS Y11, Y15, Y11                    // c441045edb
    	VDIVSD (BX), X9, X2                     // c4e1335e13 or c5b35e13
    	VDIVSD (R11), X9, X2                    // c4c1335e13
    	VDIVSD X2, X9, X2                       // c4e1335ed2 or c5b35ed2
    	VDIVSD X11, X9, X2                      // c4c1335ed3
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Oct 08 21:38:44 UTC 2021
    - 581.9K bytes
    - Viewed (0)
  6. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

    	VCTZDM:         "vctzdm",
    	VDIVESD:        "vdivesd",
    	VDIVESQ:        "vdivesq",
    	VDIVESW:        "vdivesw",
    	VDIVEUD:        "vdiveud",
    	VDIVEUQ:        "vdiveuq",
    	VDIVEUW:        "vdiveuw",
    	VDIVSD:         "vdivsd",
    	VDIVSQ:         "vdivsq",
    	VDIVSW:         "vdivsw",
    	VDIVUD:         "vdivud",
    	VDIVUQ:         "vdivuq",
    	VDIVUW:         "vdivuw",
    	VEXPANDBM:      "vexpandbm",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 334.7K bytes
    - Viewed (0)
  7. test/codegen/floats.go

    	// 386/sse2:"MULSD",-"DIVSD"
    	// amd64:"MULSD",-"DIVSD"
    	// arm/7:"MULD",-"DIVD"
    	// arm64:"FMULD",-"FDIVD"
    	// ppc64x:"FMUL",-"FDIV"
    	// riscv64:"FMULD",-"FDIVD"
    	x := f1 / 16.0
    
    	// 386/sse2:"MULSD",-"DIVSD"
    	// amd64:"MULSD",-"DIVSD"
    	// arm/7:"MULD",-"DIVD"
    	// arm64:"FMULD",-"FDIVD"
    	// ppc64x:"FMUL",-"FDIVD"
    	// riscv64:"FMULD",-"FDIVD"
    	y := f2 / 0.125
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 4.9K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/riscv/anames.go

    	"RDINSTRET",
    	"RDINSTRETH",
    	"FRCSR",
    	"FSCSR",
    	"FRRM",
    	"FSRM",
    	"FRFLAGS",
    	"FSFLAGS",
    	"FSRMI",
    	"FSFLAGSI",
    	"FLW",
    	"FSW",
    	"FADDS",
    	"FSUBS",
    	"FMULS",
    	"FDIVS",
    	"FMINS",
    	"FMAXS",
    	"FSQRTS",
    	"FMADDS",
    	"FMSUBS",
    	"FNMADDS",
    	"FNMSUBS",
    	"FCVTWS",
    	"FCVTLS",
    	"FCVTSW",
    	"FCVTSL",
    	"FCVTWUS",
    	"FCVTLUS",
    	"FCVTSWU",
    	"FCVTSLU",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/arm64/anames.go

    	"FCVTDH",
    	"FCVTDS",
    	"FCVTHD",
    	"FCVTHS",
    	"FCVTSD",
    	"FCVTSH",
    	"FCVTZSD",
    	"FCVTZSDW",
    	"FCVTZSS",
    	"FCVTZSSW",
    	"FCVTZUD",
    	"FCVTZUDW",
    	"FCVTZUS",
    	"FCVTZUSW",
    	"FDIVD",
    	"FDIVS",
    	"FLDPD",
    	"FLDPQ",
    	"FLDPS",
    	"FMADDD",
    	"FMADDS",
    	"FMAXD",
    	"FMAXNMD",
    	"FMAXNMS",
    	"FMAXS",
    	"FMIND",
    	"FMINNMD",
    	"FMINNMS",
    	"FMINS",
    	"FMOVD",
    	"FMOVQ",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  10. src/math/hypot_amd64.s

    	CMPQ    AX, CX
    	JLE     isInfOrNaN
    	// hypot = max * sqrt(1 + (min/max)**2)
    	MOVQ    BX, X0
    	MOVQ    CX, X1
    	ORQ     CX, BX
    	JEQ     isZero
    	MOVAPD  X0, X2
    	MAXSD   X1, X0
    	MINSD   X2, X1
    	DIVSD   X0, X1
    	MULSD   X1, X1
    	ADDSD   $1.0, X1
    	SQRTSD  X1, X1
    	MULSD   X1, X0
    	MOVSD   X0, ret+16(FP)
    	RET
    isInfOrNaN:
    	CMPQ    AX, BX
    	JEQ     isInf
    	CMPQ    AX, CX
    	JEQ     isInf
    	MOVQ    $NaN, AX
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 15 15:48:19 UTC 2021
    - 1.1K bytes
    - Viewed (0)
Back to top