{Name: "asimdhp", Feature: &ARM64.HasASIMDHP},
		{Name: "cpuid", Feature: &ARM64.HasCPUID},
		{Name: "asimrdm", Feature: &ARM64.HasASIMDRDM},
		{Name: "fcma", Feature: &ARM64.HasFCMA},
		{Name: "dcpop", Feature: &ARM64.HasDCPOP},
		{Name: "asimddp", Feature: &ARM64.HasASIMDDP},
		{Name: "asimdfhm", Feature: &ARM64.HasASIMDFHM},
	}
}

func archInit() {
	switch runtime.GOOS {
	case "freebsd":

	"ADDUW",
	"SH1ADD",
	"SH1ADDUW",
	"SH2ADD",
	"SH2ADDUW",
	"SH3ADD",
	"SH3ADDUW",
	"SLLIUW",
	"ANDN",
	"ORN",
	"XNOR",
	"CLZ",
	"CLZW",
	"CTZ",
	"CTZW",
	"CPOP",
	"CPOPW",
	"MAX",
	"MAXU",
	"MIN",
	"MINU",
	"SEXTB",
	"SEXTH",
	"ZEXTH",
	"ROL",
	"ROLW",
	"ROR",
	"RORI",
	"RORIW",
	"RORW",
	"ORCB",
	"REV8",
	"BCLR",

	ASH1ADD
	ASH1ADDUW
	ASH2ADD
	ASH2ADDUW
	ASH3ADD
	ASH3ADDUW
	ASLLIUW

	// 1.2: Basic Bit Manipulation (Zbb)
	AANDN
	AORN
	AXNOR
	ACLZ
	ACLZW
	ACTZ
	ACTZW
	ACPOP
	ACPOPW
	AMAX
	AMAXU
	AMIN
	AMINU
	ASEXTB
	ASEXTH
	AZEXTH

	// 1.3: Bitwise Rotation (Zbb)
	AROL
	AROLW
	AROR
	ARORI
	ARORIW
	ARORW
	AORCB
	AREV8

		return &inst{0x33, 0x1, 0x0, 640, 0x14}
	case ABSETI:
		return &inst{0x13, 0x1, 0x0, 640, 0x14}
	case ACLZ:
		return &inst{0x13, 0x1, 0x0, 1536, 0x30}
	case ACLZW:
		return &inst{0x1b, 0x1, 0x0, 1536, 0x30}
	case ACPOP:
		return &inst{0x13, 0x1, 0x2, 1538, 0x30}
	case ACPOPW:
		return &inst{0x1b, 0x1, 0x2, 1538, 0x30}
	case ACSRRC:
		return &inst{0x73, 0x3, 0x0, 0, 0x0}
	case ACSRRCI:
		return &inst{0x73, 0x7, 0x0, 0, 0x0}

	SLLIUW		$1, X18, X19			// 9b191908

	// 1.2: Basic Bit Manipulation (Zbb)
	ANDN	X19, X20, X21				// b37a3a41
	ANDN	X19, X20				// 337a3a41
	CLZ	X20, X21				// 931a0a60
	CLZW	X21, X22				// 1b9b0a60
	CPOP	X22, X23				// 931b2b60
	CPOPW	X23, X24				// 1b9c2b60
	CTZ	X24, X25				// 931c1c60
	CTZW	X25, X26				// 1b9d1c60
	MAX	X26, X28, X29				// b36eae0b
	MAX	X26, X28				// 336eae0b
	MAXU	X28, X29, X30				// 33ffce0b

	ASLLIUW & obj.AMask:   iIEncoding,

	// 1.2: Basic Bit Manipulation (Zbb)
	AANDN & obj.AMask:  rIIIEncoding,
	ACLZ & obj.AMask:   rIIEncoding,
	ACLZW & obj.AMask:  rIIEncoding,
	ACPOP & obj.AMask:  rIIEncoding,
	ACPOPW & obj.AMask: rIIEncoding,
	ACTZ & obj.AMask:   rIIEncoding,
	ACTZW & obj.AMask:  rIIEncoding,
	AMAX & obj.AMask:   rIIIEncoding,
	AMAXU & obj.AMask:  rIIIEncoding,

{"Name":"DC","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|0|1|1|1|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"DC <dc_op>, <Xt>","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
{"Name":"DCPS1","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|0|1","Arch":"System variant","Syntax":"DCPS1 {#<imm>}","Code":"","Alias":""},