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Results 1 - 6 of 6 for AANDN (0.29 sec)

  1. src/cmd/internal/obj/riscv/cpu.go

    	//
    
    	// 1.1: Address Generation Instructions (Zba)
    	AADDUW
    	ASH1ADD
    	ASH1ADDUW
    	ASH2ADD
    	ASH2ADDUW
    	ASH3ADD
    	ASH3ADDUW
    	ASLLIUW
    
    	// 1.2: Basic Bit Manipulation (Zbb)
    	AANDN
    	AORN
    	AXNOR
    	ACLZ
    	ACLZW
    	ACTZ
    	ACTZW
    	ACPOP
    	ACPOPW
    	AMAX
    	AMAXU
    	AMIN
    	AMINU
    	ASEXTB
    	ASEXTH
    	AZEXTH
    
    	// 1.3: Bitwise Rotation (Zbb)
    	AROL
    	AROLW
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/ppc64/a.out.go

    	AADDCV
    	AADDCVCC
    	AADDME
    	AADDMECC
    	AADDMEVCC
    	AADDMEV
    	AADDE
    	AADDECC
    	AADDEVCC
    	AADDEV
    	AADDZE
    	AADDZECC
    	AADDZEVCC
    	AADDZEV
    	AADDEX
    	AAND
    	AANDCC
    	AANDN
    	AANDNCC
    	AANDISCC
    	ABC
    	ABCL
    	ABEQ
    	ABGE // not LT = G/E/U
    	ABGT
    	ABLE // not GT = L/E/U
    	ABLT
    	ABNE  // not EQ = L/G/U
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 16K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/riscv/inst.go

    		return &inst{0x2f, 0x3, 0x0, 512, 0x10}
    	case AAMOXORW:
    		return &inst{0x2f, 0x2, 0x0, 512, 0x10}
    	case AAND:
    		return &inst{0x33, 0x7, 0x0, 0, 0x0}
    	case AANDI:
    		return &inst{0x13, 0x7, 0x0, 0, 0x0}
    	case AANDN:
    		return &inst{0x33, 0x7, 0x0, 1024, 0x20}
    	case AAUIPC:
    		return &inst{0x17, 0x0, 0x0, 0, 0x0}
    	case ABCLR:
    		return &inst{0x33, 0x1, 0x0, 1152, 0x24}
    	case ABCLRI:
    		return &inst{0x13, 0x1, 0x0, 1152, 0x24}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.9K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/riscv/obj.go

    			AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW,
    			AREM, AREMU, AREMW, AREMUW,
    			AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW,
    			AANDN, AORN, AXNOR, AMAX, AMAXU, AMIN, AMINU, AROL, AROLW, AROR, ARORW, ARORI, ARORIW,
    			ABCLR, ABCLRI, ABEXT, ABEXTI, ABINV, ABINVI, ABSET, ABSETI:
    			p.Reg = p.To.Reg
    		}
    	}
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/ppc64/asm9.go

    }
    
    func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
    	p := cursym.Func().Text
    	if p == nil || p.Link == nil { // handle external functions and ELF section symbols
    		return
    	}
    
    	if oprange[AANDN&obj.AMask] == nil {
    		ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first")
    	}
    
    	c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
    
    	pc := int64(0)
    	p.Pc = pc
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 13:55:28 UTC 2024
    - 156.1K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/opGen.go

    				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
    			},
    		},
    	},
    	{
    		name:   "ANDN",
    		argLen: 2,
    		asm:    ppc64.AANDN,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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