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Results 1 - 6 of 6 for ACLZW (0.25 sec)

  1. src/cmd/internal/obj/riscv/cpu.go

    	AADDUW
    	ASH1ADD
    	ASH1ADDUW
    	ASH2ADD
    	ASH2ADDUW
    	ASH3ADD
    	ASH3ADDUW
    	ASLLIUW
    
    	// 1.2: Basic Bit Manipulation (Zbb)
    	AANDN
    	AORN
    	AXNOR
    	ACLZ
    	ACLZW
    	ACTZ
    	ACTZW
    	ACPOP
    	ACPOPW
    	AMAX
    	AMAXU
    	AMIN
    	AMINU
    	ASEXTB
    	ASEXTH
    	AZEXTH
    
    	// 1.3: Bitwise Rotation (Zbb)
    	AROL
    	AROLW
    	AROR
    	ARORI
    	ARORIW
    	ARORW
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/riscv/inst.go

    		return &inst{0x63, 0x1, 0x0, 0, 0x0}
    	case ABSET:
    		return &inst{0x33, 0x1, 0x0, 640, 0x14}
    	case ABSETI:
    		return &inst{0x13, 0x1, 0x0, 640, 0x14}
    	case ACLZ:
    		return &inst{0x13, 0x1, 0x0, 1536, 0x30}
    	case ACLZW:
    		return &inst{0x1b, 0x1, 0x0, 1536, 0x30}
    	case ACPOP:
    		return &inst{0x13, 0x1, 0x2, 1538, 0x30}
    	case ACPOPW:
    		return &inst{0x1b, 0x1, 0x2, 1538, 0x30}
    	case ACSRRC:
    		return &inst{0x73, 0x3, 0x0, 0, 0x0}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.9K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/arm64/a.out.go

    	ACASLW
    	ACASPD
    	ACASPW
    	ACASW
    	ACBNZ
    	ACBNZW
    	ACBZ
    	ACBZW
    	ACCMN
    	ACCMNW
    	ACCMP
    	ACCMPW
    	ACINC
    	ACINCW
    	ACINV
    	ACINVW
    	ACLREX
    	ACLS
    	ACLSW
    	ACLZ
    	ACLZW
    	ACMN
    	ACMNW
    	ACMP
    	ACMPW
    	ACNEG
    	ACNEGW
    	ACRC32B
    	ACRC32CB
    	ACRC32CH
    	ACRC32CW
    	ACRC32CX
    	ACRC32H
    	ACRC32W
    	ACRC32X
    	ACSEL
    	ACSELW
    	ACSET
    	ACSETM
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 18 17:56:30 UTC 2023
    - 18.1K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/riscv/obj.go

    	ASH3ADDUW & obj.AMask: rIIIEncoding,
    	ASLLIUW & obj.AMask:   iIEncoding,
    
    	// 1.2: Basic Bit Manipulation (Zbb)
    	AANDN & obj.AMask:  rIIIEncoding,
    	ACLZ & obj.AMask:   rIIEncoding,
    	ACLZW & obj.AMask:  rIIEncoding,
    	ACPOP & obj.AMask:  rIIEncoding,
    	ACPOPW & obj.AMask: rIIEncoding,
    	ACTZ & obj.AMask:   rIIEncoding,
    	ACTZW & obj.AMask:  rIIEncoding,
    	AMAX & obj.AMask:   rIIIEncoding,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/arm64/asm7.go

    			oprangeset(ALSRW, t)
    			oprangeset(AASR, t)
    			oprangeset(AASRW, t)
    			oprangeset(AROR, t)
    			oprangeset(ARORW, t)
    
    		case ACLS:
    			oprangeset(ACLSW, t)
    			oprangeset(ACLZ, t)
    			oprangeset(ACLZW, t)
    			oprangeset(ARBIT, t)
    			oprangeset(ARBITW, t)
    			oprangeset(AREV, t)
    			oprangeset(AREVW, t)
    			oprangeset(AREV16, t)
    			oprangeset(AREV16W, t)
    			oprangeset(AREV32, t)
    
    		case ASDIV:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/opGen.go

    				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
    			},
    		},
    	},
    	{
    		name:   "CLZW",
    		argLen: 1,
    		asm:    arm64.ACLZW,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
    			},
    			outputs: []outputInfo{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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