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Results 1 - 3 of 3 for ASH3ADDUW (0.13 sec)

  2. github.com/golang/go

    src/cmd/internal/obj/riscv/cpu.go 

    	ASFENCEVMA

	//
	// RISC-V Bit-Manipulation ISA-extensions (1.0)
	//

	// 1.1: Address Generation Instructions (Zba)
	AADDUW
	ASH1ADD
	ASH1ADDUW
	ASH2ADD
	ASH2ADDUW
	ASH3ADD
	ASH3ADDUW
	ASLLIUW

	// 1.2: Basic Bit Manipulation (Zbb)
	AANDN
	AORN
	AXNOR
	ACLZ
	ACLZW
	ACTZ
	ACTZW
	ACPOP
	ACPOPW
	AMAX
	AMAXU
	AMIN
	AMINU
	ASEXTB
	ASEXTH
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  3. github.com/golang/go

    src/cmd/internal/obj/riscv/inst.go 

    	case ASH2ADD:
		return &inst{0x33, 0x4, 0x0, 512, 0x10}
	case ASH2ADDUW:
		return &inst{0x3b, 0x4, 0x0, 512, 0x10}
	case ASH3ADD:
		return &inst{0x33, 0x6, 0x0, 512, 0x10}
	case ASH3ADDUW:
		return &inst{0x3b, 0x6, 0x0, 512, 0x10}
	case ASLL:
		return &inst{0x33, 0x1, 0x0, 0, 0x0}
	case ASLLI:
		return &inst{0x13, 0x1, 0x0, 0, 0x0}
	case ASLLIUW:
		return &inst{0x1b, 0x1, 0x0, 128, 0x4}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.9K bytes
    - Viewed (0)
  4. github.com/golang/go

    src/cmd/internal/obj/riscv/obj.go 

    			AADD, AAND, AOR, AXOR, ASLL, ASRL, ASUB, ASRA,
			AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW,
			AREM, AREMU, AREMW, AREMUW,
			AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW,
			AANDN, AORN, AXNOR, AMAX, AMAXU, AMIN, AMINU, AROL, AROLW, AROR, ARORW, ARORI, ARORIW,
			ABCLR, ABCLRI, ABEXT, ABEXTI, ABINV, ABINVI, ABSET, ABSETI:
			p.Reg = p.To.Reg
		}
	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
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