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Results 1 - 10 of 11 for sbfiz5 (0.2 sec)

  1. test/codegen/bitfield.go

    }
    
    func sbfiz4(x int8) int64 {
    	return int64(x << 3) // arm64:"SBFIZ\t[$]3, R[0-9]+, [$]5",-"LSL"
    }
    
    // sbfiz combinations.
    // merge shift with sbfiz into sbfiz.
    func sbfiz5(x int32) int32 {
    	// arm64:"SBFIZ\t[$]1, R[0-9]+, [$]28",-"LSL",-"ASR"
    	return (x << 4) >> 3
    }
    
    func sbfiz6(x int16) int64 {
    	return int64(x+1) << 3 // arm64:"SBFIZ\t[$]3, R[0-9]+, [$]16",-"LSL"
    }
    
    func sbfiz7(x int8) int64 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 23 06:11:32 UTC 2022
    - 9.6K bytes
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  2. src/cmd/internal/obj/arm64/anames.go

    	"PRFUM",
    	"RBIT",
    	"RBITW",
    	"REM",
    	"REMW",
    	"REV",
    	"REV16",
    	"REV16W",
    	"REV32",
    	"REVW",
    	"ROR",
    	"RORW",
    	"SBC",
    	"SBCS",
    	"SBCSW",
    	"SBCW",
    	"SBFIZ",
    	"SBFIZW",
    	"SBFM",
    	"SBFMW",
    	"SBFX",
    	"SBFXW",
    	"SCVTFD",
    	"SCVTFS",
    	"SCVTFWD",
    	"SCVTFWS",
    	"SDIV",
    	"SDIVW",
    	"SEV",
    	"SEVL",
    	"SHA1C",
    	"SHA1H",
    	"SHA1M",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/arm64/doc.go

    	FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
    	FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25
    
    (4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd>
    
    Examples:
    
    	BFIW $16, R20, $6, R0      <=>    bfi w0, w20, #16, #6
    	UBFIZ $34, R26, $5, R20    <=>    ubfiz x20, x26, #34, #5
    
    (5) FCCMPD, FCCMPS, FCCMPED, FCCMPES <cond>, Fm. Fn, $<nzcv>
    
    Examples:
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Aug 07 00:21:42 UTC 2023
    - 9.6K bytes
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  4. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    // bitfield ops
    
    // sbfiz
    // (x << lc) >> rc
    (SRAconst [rc] (SLLconst [lc] x)) && lc > rc => (SBFIZ [armBFAuxInt(lc-rc, 64-lc)] x)
    // int64(x << lc)
    (MOVWreg (SLLconst [lc] x)) && lc < 32 => (SBFIZ [armBFAuxInt(lc, 32-lc)] x)
    (MOVHreg (SLLconst [lc] x)) && lc < 16 => (SBFIZ [armBFAuxInt(lc, 16-lc)] x)
    (MOVBreg (SLLconst [lc] x)) && lc < 8  => (SBFIZ [armBFAuxInt(lc,  8-lc)] x)
    // int64(x) << lc
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
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  5. src/cmd/internal/obj/arm64/a.out.go

    	AORR
    	AORRW
    	APRFM
    	APRFUM
    	ARBIT
    	ARBITW
    	AREM
    	AREMW
    	AREV
    	AREV16
    	AREV16W
    	AREV32
    	AREVW
    	AROR
    	ARORW
    	ASBC
    	ASBCS
    	ASBCSW
    	ASBCW
    	ASBFIZ
    	ASBFIZW
    	ASBFM
    	ASBFMW
    	ASBFX
    	ASBFXW
    	ASCVTFD
    	ASCVTFS
    	ASCVTFWD
    	ASCVTFWS
    	ASDIV
    	ASDIVW
    	ASEV
    	ASEVL
    	ASHA1C
    	ASHA1H
    	ASHA1M
    	ASHA1P
    	ASHA1SU0
    	ASHA1SU1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 18 17:56:30 UTC 2023
    - 18.1K bytes
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  6. src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go

    			if rno <= uint16(WZR) {
    				op += "W"
    			}
    		}
    		args[1], args[2] = args[2], args[1]
    
    	case STLXRB, STLXRH, STXRB, STXRH:
    		args[1], args[2] = args[2], args[1]
    
    	case BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX:
    		if r, ok := inst.Args[0].(Reg); ok {
    			rno := uint16(r)
    			if rno <= uint16(WZR) {
    				op += "W"
    			}
    		}
    		args[1], args[2], args[3] = args[3], args[1], args[2]
    
    	case LDAXP, LDXP:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 16 22:24:28 UTC 2022
    - 17K bytes
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  7. src/cmd/compile/internal/ssa/rewriteARM64.go

    			break
    		}
    		v.reset(OpARM64SBFX)
    		v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8-rc))
    		v.AddArg(x)
    		return true
    	}
    	// match: (SRAconst [sc] (SBFIZ [bfc] x))
    	// cond: sc < bfc.getARM64BFlsb()
    	// result: (SBFIZ [armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())] x)
    	for {
    		sc := auxIntToInt64(v.AuxInt)
    		if v_0.Op != OpARM64SBFIZ {
    			break
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 608.6K bytes
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  8. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	SBC R25, R10, R26                          // 5a0119da
    	SBCSW R27, R19, R19                        // 73021b7a
    	SBCS R5, R9, R5                            // 250105fa
    	SBFIZW $9, R10, $18, R22                   // 56451713
    	SBFIZ $6, R11, $15, R20                    // 74397a93
    	SBFXW $8, R15, $10, R20                    // f4450813
    	SBFX $2, R27, $54, R7                      // 67df4293
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
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  9. src/cmd/internal/obj/arm64/asm7.go

    			oprangeset(ASBFMW, t)
    			oprangeset(AUBFM, t)
    			oprangeset(AUBFMW, t)
    
    		case ABFI:
    			oprangeset(ABFIW, t)
    			oprangeset(ABFXIL, t)
    			oprangeset(ABFXILW, t)
    			oprangeset(ASBFIZ, t)
    			oprangeset(ASBFIZW, t)
    			oprangeset(ASBFX, t)
    			oprangeset(ASBFXW, t)
    			oprangeset(AUBFIZ, t)
    			oprangeset(AUBFIZW, t)
    			oprangeset(AUBFX, t)
    			oprangeset(AUBFXW, t)
    
    		case AEXTR:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
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  10. src/cmd/asm/internal/asm/testdata/arm64.s

    	STPW	(R3, R4), x+8(SB)
    
    // bit field operation
    	BFI	$0, R1, $1, R2      // 220040b3
    	BFIW	$0, R1, $1, R2      // 22000033
    	SBFIZ	$0, R1, $1, R2      // 22004093
    	SBFIZW	$0, R1, $1, R2      // 22000013
    	UBFIZ	$0, R1, $1, R2      // 220040d3
    	UBFIZW	$0, R1, $1, R2      // 22000053
    
    // FSTPD/FSTPS/FLDPD/FLDPS
    	FLDPD	(R0), (F1, F2)      // 0108406d
    	FLDPD	8(R0), (F1, F2)     // 0188406d
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 94.9K bytes
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