}

func sbfiz4(x int8) int64 {
	return int64(x << 3) // arm64:"SBFIZ\t[$]3, R[0-9]+, [$]5",-"LSL"
}

// sbfiz combinations.
// merge shift with sbfiz into sbfiz.
func sbfiz5(x int32) int32 {
	// arm64:"SBFIZ\t[$]1, R[0-9]+, [$]28",-"LSL",-"ASR"
	return (x << 4) >> 3
}

func sbfiz6(x int16) int64 {
	return int64(x+1) << 3 // arm64:"SBFIZ\t[$]3, R[0-9]+, [$]16",-"LSL"
}

func sbfiz7(x int8) int64 {

	"PRFUM",
	"RBIT",
	"RBITW",
	"REM",
	"REMW",
	"REV",
	"REV16",
	"REV16W",
	"REV32",
	"REVW",
	"ROR",
	"RORW",
	"SBC",
	"SBCS",
	"SBCSW",
	"SBCW",
	"SBFIZ",
	"SBFIZW",
	"SBFM",
	"SBFMW",
	"SBFX",
	"SBFXW",
	"SCVTFD",
	"SCVTFS",
	"SCVTFWD",
	"SCVTFWS",
	"SDIV",
	"SDIVW",
	"SEV",
	"SEVL",
	"SHA1C",
	"SHA1H",
	"SHA1M",

	FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
	FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25

(4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd>

Examples:

	BFIW $16, R20, $6, R0      <=>    bfi w0, w20, #16, #6
	UBFIZ $34, R26, $5, R20    <=>    ubfiz x20, x26, #34, #5

(5) FCCMPD, FCCMPS, FCCMPED, FCCMPES <cond>, Fm. Fn, $<nzcv>

Examples:

// bitfield ops

// sbfiz
// (x << lc) >> rc
(SRAconst [rc] (SLLconst [lc] x)) && lc > rc => (SBFIZ [armBFAuxInt(lc-rc, 64-lc)] x)
// int64(x << lc)
(MOVWreg (SLLconst [lc] x)) && lc < 32 => (SBFIZ [armBFAuxInt(lc, 32-lc)] x)
(MOVHreg (SLLconst [lc] x)) && lc < 16 => (SBFIZ [armBFAuxInt(lc, 16-lc)] x)
(MOVBreg (SLLconst [lc] x)) && lc < 8  => (SBFIZ [armBFAuxInt(lc,  8-lc)] x)
// int64(x) << lc

	SADALP:    "SADALP",
	SADDL:     "SADDL",
	SADDL2:    "SADDL2",
	SADDLP:    "SADDLP",
	SADDLV:    "SADDLV",
	SADDW:     "SADDW",
	SADDW2:    "SADDW2",
	SBC:       "SBC",
	SBCS:      "SBCS",
	SBFIZ:     "SBFIZ",
	SBFM:      "SBFM",
	SBFX:      "SBFX",
	SCVTF:     "SCVTF",
	SDIV:      "SDIV",
	SEV:       "SEV",
	SEVL:      "SEVL",
	SHA1C:     "SHA1C",
	SHA1H:     "SHA1H",
	SHA1M:     "SHA1M",

	AORR
	AORRW
	APRFM
	APRFUM
	ARBIT
	ARBITW
	AREM
	AREMW
	AREV
	AREV16
	AREV16W
	AREV32
	AREVW
	AROR
	ARORW
	ASBC
	ASBCS
	ASBCSW
	ASBCW
	ASBFIZ
	ASBFIZW
	ASBFM
	ASBFMW
	ASBFX
	ASBFXW
	ASCVTFD
	ASCVTFS
	ASCVTFWD
	ASCVTFWS
	ASDIV
	ASDIVW
	ASEV
	ASEVL
	ASHA1C
	ASHA1H
	ASHA1M
	ASHA1P
	ASHA1SU0
	ASHA1SU1

			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[1], args[2] = args[2], args[1]

	case STLXRB, STLXRH, STXRB, STXRH:
		args[1], args[2] = args[2], args[1]

	case BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX:
		if r, ok := inst.Args[0].(Reg); ok {
			rno := uint16(r)
			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[1], args[2], args[3] = args[3], args[1], args[2]

	case LDAXP, LDXP:

			break
		}
		v.reset(OpARM64SBFX)
		v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8-rc))
		v.AddArg(x)
		return true
	}
	// match: (SRAconst [sc] (SBFIZ [bfc] x))
	// cond: sc < bfc.getARM64BFlsb()
	// result: (SBFIZ [armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())] x)
	for {
		sc := auxIntToInt64(v.AuxInt)
		if v_0.Op != OpARM64SBFIZ {
			break
		}

	SBC R25, R10, R26                          // 5a0119da
	SBCSW R27, R19, R19                        // 73021b7a
	SBCS R5, R9, R5                            // 250105fa
	SBFIZW $9, R10, $18, R22                   // 56451713
	SBFIZ $6, R11, $15, R20                    // 74397a93
	SBFXW $8, R15, $10, R20                    // f4450813
	SBFX $2, R27, $54, R7                      // 67df4293

			oprangeset(ASBFMW, t)
			oprangeset(AUBFM, t)
			oprangeset(AUBFMW, t)

		case ABFI:
			oprangeset(ABFIW, t)
			oprangeset(ABFXIL, t)
			oprangeset(ABFXILW, t)
			oprangeset(ASBFIZ, t)
			oprangeset(ASBFIZW, t)
			oprangeset(ASBFX, t)
			oprangeset(ASBFXW, t)
			oprangeset(AUBFIZ, t)
			oprangeset(AUBFIZW, t)
			oprangeset(AUBFX, t)
			oprangeset(AUBFXW, t)

		case AEXTR: