VSETVLI	X10, E32, MF8, TA, MA, X12		// 5776550d
	VSETVLI	X10, E32, MF4, TA, MA, X12		// 5776650d
	VSETVLI	X10, E32, MF2, TA, MA, X12		// 5776750d
	VSETVLI	X10, E32, M1, TA, MA, X12		// 5776050d
	VSETVLI	$15, E32, M1, TA, MA, X12		// 57f607cd
	VSETIVLI $0, E32, M1, TA, MA, X12		// 577600cd
	VSETIVLI $15, E32, M1, TA, MA, X12		// 57f607cd
	VSETIVLI $31, E32, M1, TA, MA, X12		// 57f60fcd
	VSETVL	X10, X11, X12				// 57f6a580

	VGATHERQPS X2, (BP)(Y7*2), X1           // c4e26d934c7d00
	VGATHERQPS X12, (R13)(X14*2), X11       // c40219935c7500
	VGATHERQPS X12, (R13)(Y14*2), X11       // c4021d935c7500
	VGATHERQPS X2, (BP)(X7*2), X1           // c4e269934c7d00
	VGATHERQPS X2, (BP)(Y7*2), X1           // c4e26d934c7d00
	VGATHERQPS X12, (R13)(X14*2), X11       // c40219935c7500
	VGATHERQPS X12, (R13)(Y14*2), X11       // c4021d935c7500

MOVOU 80(DI), X12 PCLMULQDQ $0x00, X2, X12 PXOR X12, X10 MOVOU 96(DI), X12 MOVOU X12, X13 PCLMULQDQ $0x00, X3, X12 PXOR X12, X8 PCLMULQDQ $0x11, X3, X13 PXOR X13, X9 PSHUFD $0x4e, X3, X12 PXOR X12, X3 MOVOU 112(DI), X12 PCLMULQDQ $0x00, X3, X12 PXOR X12, X10 MOVOU 128(DI), X12 MOVOU X12, X13 PCLMULQDQ $0x00, X4, X12 PXOR X12, X8 PCLMULQDQ $0x11, X4, X13 PXOR X13, X9 PSHUFD $0x4e, X4, X12 PXOR X12, X4 MOVOU 144(DI), X12 PCLMULQDQ $0x00, X4, X12 PXOR X12, X10 MOVOU 160(DI), X12 MOVOU X12, X13 PCLMULQDQ...

	EXTRACTPS $4, X2, (BX)          // ERROR "invalid instruction"
	EXTRACTPS $-1, X2, (BX)         // ERROR "invalid instruction"
	// VSIB addressing does not permit non-vector (X/Y)
	// scaled index register.
	VPGATHERDQ X12,(R13)(AX*2), X11 // ERROR "invalid instruction"
	VPGATHERDQ X2, 664(BX*1), X1    // ERROR "invalid instruction"
	VPGATHERDQ Y2, (BP)(AX*2), Y1   // ERROR "invalid instruction"

	//
	// "V" Standard Extension for Vector Operations, Version 1.0
	//
	VSETVLI		$32, E16, M1, TU, MU, X12	// ERROR "must be in range [0, 31] (5 bits)"
	VSETVLI		$-1, E32, M2, TA, MA, X12	// ERROR "must be in range [0, 31] (5 bits)"
	VSETVL		X10, X11			// ERROR "expected integer register in rs1 position"
	VLE8V		(X10), X10			// ERROR "expected vector register in vd position"

	MOVWU	X5, (X6)			// ERROR "unsupported unsigned store"
	MOVF	F0, F1, F2			// ERROR "illegal MOV instruction"
	MOVD	F0, F1, F2			// ERROR "illegal MOV instruction"
	MOV	X10, X11, X12			// ERROR "illegal MOV instruction"
	MOVW	X10, X11, X12			// ERROR "illegal MOV instruction"
	RORI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
	SLLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"

	{"R14", "R14"},
	{"R15", "R15"},
	{"R8", "R8"},
	{"R9", "R9"},
	{"g", "R14"},
	{"SI", "SI"},
	{"SP", "SP"},
	{"X0", "X0"},
	{"X1", "X1"},
	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},
	{"X15", "X15"},
	{"X2", "X2"},
	{"X3", "X3"},
	{"X4", "X4"},
	{"X5", "X5"},
	{"X6", "X6"},
	{"X7", "X7"},
	{"X8", "X8"},
	{"X9", "X9"},

    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,
    X22,
    X23,
    X24,
    X25,
    X26,
    X27,
    X28,
    X29,