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Results 1 - 10 of 23 for r26 (0.02 sec)

  1. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	AND $-9223372036854775808, R1, R1          // 21004192
    	ANDW $4026540031, R29, R2                  // a2430412
    	AND $34903429696192636, R12, R19           // 93910e92
    	ANDW R9@>7, R19, R26                       // 7a1ec90a
    	AND R9@>7, R19, R26                        // 7a1ec98a
    	TSTW $2863311530, R24                      // 1ff30172
    	TST R2, R0                                 // 1f0002ea
    	TST $7, R2                                 // 5f0840f2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/mips64.s

    	ADD	$-7193, R24	// 2318e3e7
    	ADDV	$-7193, R24	// 6318e3e7
    
    //	LSUBW rreg ',' sreg ',' rreg
    //	{
    //		outcode(int($1), &$2, int($4), &$6);
    //	}
    	SUB	R6, R26, R27	// 0346d822
    	SUBU	R6, R26, R27	// 0346d823
    	SUBV	R16, R17, R26	// 0230d02e
    	SUBVU	R16, R17, R26	// 0230d02f
    
    //	LSUBW imm ',' sreg ',' rreg
    //	{
    //		outcode(int($1), &$2, int($4), &$6);
    //	}
    	SUB	$-3126, R17, R22	// 22360c36
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/operand_test.go

    	{"R16", "R16"},
    	{"R17", "R17"},
    	{"R18", "R18"},
    	{"R19", "R19"},
    	{"R2", "R2"},
    	{"R20", "R20"},
    	{"R21", "R21"},
    	{"R22", "R22"},
    	{"R23", "R23"},
    	{"R24", "R24"},
    	{"R25", "R25"},
    	{"R26", "R26"},
    	{"R27", "R27"},
    	{"R28", "R28"},
    	{"R29", "R29"},
    	{"R3", "R3"},
    	{"R31", "R31"},
    	{"R4", "R4"},
    	{"R5", "R5"},
    	{"R6", "R6"},
    	{"R7", "R7"},
    	{"R8", "R8"},
    	{"R9", "R9"},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 29 18:31:05 UTC 2023
    - 23.9K bytes
    - Viewed (0)
  4. src/hash/crc32/crc32_ppc64le.s

    	ADD	$1024,R10,R10	// &tab[5]
    	SLD	$2,R24,R24	// crc>>16&0xFF*4
    	MOVWZ	(R10)(R24),R26	// tab[5][crc>>16&0xFF]
    	XOR	R21,R26,R21	// xor done R26
    	RLDICL	$56,R7,$56,R25	// crc>>8
    	ADD	$1024,R10,R10	// &tab[6]
    	SLD	$2,R25,R25	// crc>>8&FF*2
    	MOVBZ   R7,R26          // crc&0xFF
    	MOVWZ	(R10)(R25),R27	// tab[6][crc>>8&0xFF]
    	ADD 	$1024,R10,R10   // &tab[7]
    	SLD	$2,R26,R26	// crc&0xFF*2
    	XOR	R21,R27,R21	// xor done R27
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 06 12:09:50 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  5. src/runtime/asm_arm64.s

    	// Using a tail call here cleans up tracebacks since we won't stop
    	// at an intermediate systemstack.
    	MOVD	0(R26), R3	// code pointer
    	MOVD.P	16(RSP), R30	// restore LR
    	SUB	$8, RSP, R29	// restore FP
    	B	(R3)
    
    // func switchToCrashStack0(fn func())
    TEXT runtime·switchToCrashStack0<ABIInternal>(SB), NOSPLIT, $0-8
    	MOVD	R0, R26    // context register
    	MOVD	g_m(g), R1 // curm
    
    	// set g to gcrash
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat May 11 20:38:24 UTC 2024
    - 43.4K bytes
    - Viewed (0)
  6. src/math/big/arith_ppc64x.s

    	MOVDU 32(R8), R23	// R23 = x[i+3]
    	ADDZE R20, R24		// R24 = x[i] + CA
    	ADDZE R21, R25		// R25 = x[i+1] + CA
    	ADDZE R22, R26		// R26 = x[i+2] + CA
    	ADDZE R23, R27		// R27 = x[i+3] + CA
    	MOVD  R24, 8(R10)	// z[i]
    	MOVD  R25, 16(R10)	// z[i+1]
    	MOVD  R26, 24(R10)	// z[i+2]
    	MOVDU R27, 32(R10)	// z[i+3]
    	ADD   $-4, R11		// R11 = z_len - 4
    	BDNZ  loop
    
    	// We may have some elements to read
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 18:17:17 UTC 2024
    - 16.8K bytes
    - Viewed (0)
  7. src/runtime/asm_ppc64x.s

    	BR	restore
    
    good:
    #define DEBUG_CALL_DISPATCH(NAME,MAXSIZE)	\
    	MOVD	$MAXSIZE, R23;			\
    	CMP	R26, R23;			\
    	BGT	5(PC);				\
    	MOVD	$NAME(SB), R26;			\
    	MOVD	R26, 32(R1);			\
    	CALL	runtime·debugCallWrap(SB);	\
    	BR	restore
    
    	// the argument frame size
    	MOVD	128(R1), R26
    
    	DEBUG_CALL_DISPATCH(debugCall32<>, 32)
    	DEBUG_CALL_DISPATCH(debugCall64<>, 64)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 18:17:17 UTC 2024
    - 45.4K bytes
    - Viewed (0)
  8. src/runtime/mkpreempt.go

    	p("MOVW.P %d(R13), R15", lfp.stack+4) // load PC, pop frame (including the space pushed by sigctxt.pushCall)
    	p("UNDEF")                            // shouldn't get here
    }
    
    func genARM64() {
    	// Add integer registers R0-R26
    	// R27 (REGTMP), R28 (g), R29 (FP), R30 (LR), R31 (SP) are special
    	// and not saved here.
    	var l = layout{sp: "RSP", stack: 8} // add slot to save PC of interrupted instruction
    	for i := 0; i < 26; i += 2 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 15.3K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    	"R6",
    	"R7",
    	"R8",
    	"R9",
    	"R10",
    	"R11",
    	"R12",
    	"R13",
    	"R14",
    	"R15",
    	"R16",
    	"R17",
    	"R18",
    	"R19",
    	"R20",
    	"R21",
    	"g", // aka R22
    	"R23",
    	"R24",
    	"R25",
    	"R26",
    	"R27",
    	"R28",
    	"R29",
    	// R30 is REGTMP not used in regalloc
    	"R31",
    
    	"F0",
    	"F1",
    	"F2",
    	"F3",
    	"F4",
    	"F5",
    	"F6",
    	"F7",
    	"F8",
    	"F9",
    	"F10",
    	"F11",
    	"F12",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  10. src/crypto/sha512/sha512block_ppc64x.s

    #define END	R5
    #define TBL	R6
    #define CNT	R8
    #define LEN	R9
    #define TEMP	R12
    
    #define TBL_STRT R7 // Pointer to start of kcon table.
    
    #define R_x000	R0
    #define R_x010	R10
    #define R_x020	R25
    #define R_x030	R26
    #define R_x040	R14
    #define R_x050	R15
    #define R_x060	R16
    #define R_x070	R17
    #define R_x080	R18
    #define R_x090	R19
    #define R_x0a0	R20
    #define R_x0b0	R21
    #define R_x0c0	R22
    #define R_x0d0	R23
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 15.8K bytes
    - Viewed (0)
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