// arm/7:"ADDD",-"MULD"
	// arm64:"FADDD",-"FMULD"
	// ppc64x:"FADD",-"FMUL"
	// riscv64:"FADDD",-"FMULD"
	return f * 2.0
}

func DivPow2(f1, f2, f3 float64) (float64, float64, float64) {
	// 386/sse2:"MULSD",-"DIVSD"
	// amd64:"MULSD",-"DIVSD"
	// arm/7:"MULD",-"DIVD"
	// arm64:"FMULD",-"FDIVD"
	// ppc64x:"FMUL",-"FDIV"
	// riscv64:"FMULD",-"FDIVD"
	x := f1 / 16.0

	// 386/sse2:"MULSD",-"DIVSD"

		return true
	}
	return false
}

// IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is
// one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
func IsMIPSMUL(op obj.As) bool {
	switch op {
	case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU,
		mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU,
		mips.AREM, mips.AREMU, mips.AREMV, mips.AREMVU,
		mips.AMADD, mips.AMSUB:

	LDGR	R2, F0
	FMADD	F0, F4, F0
	MOVD	$·expx4ff<>+0(SB), R3
	FMOVD	0(R3), F2
	FMUL	F2, F0
	FMOVD	F0, ret+8(FP)
	RET
L13:
	FMOVD	$0, F0
	FMOVD	F0, ret+8(FP)
	RET
L21:
	ADDW	$0x1000, R1
	RISBGN	$0, $15, $48, R1, R2
	LDGR	R2, F0
	FMADD	F0, F4, F0
	MOVD	$·expx2ff<>+0(SB), R3
	FMOVD	0(R3), F2
	FMUL	F2, F0
	FMOVD	F0, ret+8(FP)
	RET
LEXITTAGexp:
	FMOVD	F0, ret+8(FP)

	BEQ     L9
	WFMSDB  V0, V1, V6, V0
	MOVD    $sinhx4ff<>+0(SB), R3
	FNEG    F0, F0
	FMOVD   0(R3), F2
	FMUL    F2, F0
	ANDW    $0xFFFF, R2
	WORD    $0xA53FEFB6     //llill %r3,61366
	SUBW    R2, R3, R2
	RISBGN	$0, $15, $48, R2, R1
	LDGR    R1, F2
	FMUL    F2, F0
	FMOVD   F0, ret+8(FP)
	RET

L20:
	MOVD    $sinhxadd<>+0(SB), R2
	FMOVD   0(R2), F2
	MOVD    sinhrlog2<>+0(SB), R2

	"FMULSF",
	"FMULSD",
	"FNMULSF",
	"FNMULSD",
	"DIVF",
	"DIVD",
	"SQRTF",
	"SQRTD",
	"ABSF",
	"ABSD",
	"NEGF",
	"NEGD",
	"SRL",
	"SRA",
	"SLL",
	"MULU",
	"DIVU",
	"MUL",
	"MMUL",
	"DIV",
	"MOD",
	"MODU",
	"DIVHW",
	"DIVUHW",
	"MOVB",
	"MOVBS",
	"MOVBU",
	"MOVH",
	"MOVHS",
	"MOVHU",
	"MOVW",
	"MOVM",
	"SWPBU",
	"SWPW",
	"RFE",
	"SWI",

Eugene Burmako <******@****.***> 1671166704 -0800

	MOVW	R1, R7
	CMPBGT	R7, $22, L17
	LTDBR	F0, F0
	MOVD	$·logx43f<>+0(SB), R1
	FMOVD	0(R1), F2
	BLEU	L3
	MOVH	$0x8005, R12
	MOVH	$0x8405, R0
	BR	L15
L7:
	LTDBR	F0, F0
	BLEU	L3
L15:
	FMUL	F2, F0
	LGDR	F0, R1
	SRAD	$48, R1, R1
	SUBW	R1, R0, R2
	SUBW	R1, R12, R3
	BYTE	$0x18	//lr	%r4,%r2
	BYTE	$0x42
	ANDW	$0xFFFFFFF0, R3
	ANDW	$0xFFFFFFF0, R2
	BYTE	$0x18	//lr	%r5,%r1
	BYTE	$0x51

	FMOVD	296(R5), F3
	WFMADB	V1, V2, V3, V2
	FMOVD	288(R5), F3
	WFMADB	V1, V4, V3, V4
	FMOVD	280(R5), F3
	WFMADB	V1, V2, V3, V2
	FMOVD	272(R5), F3
	WFMADB	V1, V4, V3, V4
L9:
	FMOVD	264(R5), F3
	FMUL	F4, F6
	FMOVD	256(R5), F4
	WFMADB	V1, V4, V3, V4
	FDIV	F6, F2
	LGDR	F4, R1
	FSUB	F3, F4
	FMOVD	248(R5), F6
	WFMSDB	V4, V6, V1, V4
	FMOVD	240(R5), F1
	FMOVD	232(R5), F6
	WFMADB	V4, V6, V1, V6

		return true
	}
	return false
}

// IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is
// one of the MUL/DIV/REM instructions that require special handling.
func IsLoong64MUL(op obj.As) bool {
	switch op {
	case loong64.AMUL, loong64.AMULU, loong64.AMULV, loong64.AMULVU,
		loong64.ADIV, loong64.ADIVU, loong64.ADIVV, loong64.ADIVVU,
		loong64.AREM, loong64.AREMU, loong64.AREMV, loong64.AREMVU:

		t.Errorf("line number missing in assembly:\n%s", out)
	}
}

var issue16214src = `
package main

func Mod32(x uint32) uint32 {
	return x % 3 // frontend rewrites it as HMUL with 2863311531, the LITERAL node has unknown Pos
}