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Results 1 - 10 of 285 for Xmul (0.04 sec)

  1. test/chan/powser1.go

    //	then UV = u*v + x*(u*VV+v*UU) + x*x*UU*VV
    
    func Mul(U, V PS) PS {
    	Z := mkPS()
    	go func() {
    		<-Z.req
    		uv := get2(U, V)
    		if end(uv[0]) != 0 || end(uv[1]) != 0 {
    			Z.dat <- finis
    		} else {
    			Z.dat <- mul(uv[0], uv[1])
    			UU := Split(U)
    			VV := Split(V)
    			W := Add(Cmul(uv[0], VV[0]), Cmul(uv[1], UU[0]))
    			<-Z.req
    			Z.dat <- get(W)
    			copy(Add(W, Mul(UU[1], VV[1])), Z)
    		}
    	}()
    	return Z
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 25 22:22:20 UTC 2020
    - 12.7K bytes
    - Viewed (0)
  2. test/chan/powser2.go

    //	then UV = u*v + x*(u*VV+v*UU) + x*x*UU*VV
    
    func Mul(U, V PS) PS {
    	Z := mkPS()
    	go func(U, V, Z PS) {
    		<-Z.req
    		uv := get2(U, V)
    		if end(uv[0].(*rat)) != 0 || end(uv[1].(*rat)) != 0 {
    			Z.dat <- finis
    		} else {
    			Z.dat <- mul(uv[0].(*rat), uv[1].(*rat))
    			UU := Split(U)
    			VV := Split(V)
    			W := Add(Cmul(uv[0].(*rat), VV[0]), Cmul(uv[1].(*rat), UU[0]))
    			<-Z.req
    			Z.dat <- get(W)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 25 22:22:20 UTC 2020
    - 13.3K bytes
    - Viewed (0)
  3. test/codegen/floats.go

    	// arm/7:"ADDD",-"MULD"
    	// arm64:"FADDD",-"FMULD"
    	// ppc64x:"FADD",-"FMUL"
    	// riscv64:"FADDD",-"FMULD"
    	return f * 2.0
    }
    
    func DivPow2(f1, f2, f3 float64) (float64, float64, float64) {
    	// 386/sse2:"MULSD",-"DIVSD"
    	// amd64:"MULSD",-"DIVSD"
    	// arm/7:"MULD",-"DIVD"
    	// arm64:"FMULD",-"FDIVD"
    	// ppc64x:"FMUL",-"FDIV"
    	// riscv64:"FMULD",-"FDIVD"
    	x := f1 / 16.0
    
    	// 386/sse2:"MULSD",-"DIVSD"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 4.9K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/arch/mips.go

    		return true
    	}
    	return false
    }
    
    // IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is
    // one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
    func IsMIPSMUL(op obj.As) bool {
    	switch op {
    	case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU,
    		mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU,
    		mips.AREM, mips.AREMU, mips.AREMV, mips.AREMVU,
    		mips.AMADD, mips.AMSUB:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 04 19:06:44 UTC 2020
    - 1.7K bytes
    - Viewed (0)
  5. src/math/exp_s390x.s

    	LDGR	R2, F0
    	FMADD	F0, F4, F0
    	MOVD	$·expx4ff<>+0(SB), R3
    	FMOVD	0(R3), F2
    	FMUL	F2, F0
    	FMOVD	F0, ret+8(FP)
    	RET
    L13:
    	FMOVD	$0, F0
    	FMOVD	F0, ret+8(FP)
    	RET
    L21:
    	ADDW	$0x1000, R1
    	RISBGN	$0, $15, $48, R1, R2
    	LDGR	R2, F0
    	FMADD	F0, F4, F0
    	MOVD	$·expx2ff<>+0(SB), R3
    	FMOVD	0(R3), F2
    	FMUL	F2, F0
    	FMOVD	F0, ret+8(FP)
    	RET
    LEXITTAGexp:
    	FMOVD	F0, ret+8(FP)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 15:34:41 UTC 2019
    - 4.6K bytes
    - Viewed (0)
  6. src/math/sinh_s390x.s

    	BEQ     L9
    	WFMSDB  V0, V1, V6, V0
    	MOVD    $sinhx4ff<>+0(SB), R3
    	FNEG    F0, F0
    	FMOVD   0(R3), F2
    	FMUL    F2, F0
    	ANDW    $0xFFFF, R2
    	WORD    $0xA53FEFB6     //llill %r3,61366
    	SUBW    R2, R3, R2
    	RISBGN	$0, $15, $48, R2, R1
    	LDGR    R1, F2
    	FMUL    F2, F0
    	FMOVD   F0, ret+8(FP)
    	RET
    
    L20:
    	MOVD    $sinhxadd<>+0(SB), R2
    	FMOVD   0(R2), F2
    	MOVD    sinhrlog2<>+0(SB), R2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 17 13:54:10 UTC 2021
    - 6K bytes
    - Viewed (0)
  7. src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/tables.go

    	// FMUL <Sd>, <Sn>, <Sm>
    	{0xffe0fc00, 0x1e200800, FMUL, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
    	// FMUL <Dd>, <Dn>, <Dm>
    	{0xffe0fc00, 0x1e600800, FMUL, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
    	// FMUL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Aug 16 17:57:48 UTC 2017
    - 211.8K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/arm/anames.go

    	"FMULSF",
    	"FMULSD",
    	"FNMULSF",
    	"FNMULSD",
    	"DIVF",
    	"DIVD",
    	"SQRTF",
    	"SQRTD",
    	"ABSF",
    	"ABSD",
    	"NEGF",
    	"NEGD",
    	"SRL",
    	"SRA",
    	"SLL",
    	"MULU",
    	"DIVU",
    	"MUL",
    	"MMUL",
    	"DIV",
    	"MOD",
    	"MODU",
    	"DIVHW",
    	"DIVUHW",
    	"MOVB",
    	"MOVBS",
    	"MOVBU",
    	"MOVH",
    	"MOVHS",
    	"MOVHU",
    	"MOVW",
    	"MOVM",
    	"SWPBU",
    	"SWPW",
    	"RFE",
    	"SWI",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 16 15:58:33 UTC 2019
    - 1.4K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/lite/stablehlo/tests/legalize-tfl-stablehlo-mul.mlir

    Eugene Burmako <******@****.***> 1671166704 -0800
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Dec 16 05:09:09 UTC 2022
    - 751 bytes
    - Viewed (0)
  10. src/math/erfc_s390x.s

    	WFDDB	V1, V3, V6
    	VLEG	$0, 768(R9), V18
    	FMOVD	760(R9), F7
    	FMOVD	752(R9), F5
    	VLEG	$0, 744(R9), V16
    	FMOVD	736(R9), F3
    	FMOVD	728(R9), F2
    	FMOVD	720(R9), F4
    	WFMDB	V6, V6, V1
    	FMUL	F0, F0
    	MOVH	$0x0, R3
    	WFMADB	V1, V7, V20, V7
    	WFMADB	V1, V5, V18, V5
    	WFMADB	V1, V7, V16, V7
    	WFMADB	V1, V5, V3, V5
    	WFMADB	V1, V7, V4, V7
    	WFMADB	V1, V5, V2, V5
    	FMOVD	712(R9), F2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 15:34:41 UTC 2019
    - 14.4K bytes
    - Viewed (0)
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