func (c *sigctxt) r23() uint64 { return c.regs().sc_regs[23] }
func (c *sigctxt) r24() uint64 { return c.regs().sc_regs[24] }
func (c *sigctxt) r25() uint64 { return c.regs().sc_regs[25] }
func (c *sigctxt) r26() uint64 { return c.regs().sc_regs[26] }
func (c *sigctxt) r27() uint64 { return c.regs().sc_regs[27] }
func (c *sigctxt) r28() uint64 { return c.regs().sc_regs[28] }
func (c *sigctxt) r29() uint64 { return c.regs().sc_regs[29] }

func (c *sigctxt) r24() uint32       { return uint32(c.regs().sc_regs[24]) }
func (c *sigctxt) r25() uint32       { return uint32(c.regs().sc_regs[25]) }
func (c *sigctxt) r26() uint32       { return uint32(c.regs().sc_regs[26]) }
func (c *sigctxt) r27() uint32       { return uint32(c.regs().sc_regs[27]) }
func (c *sigctxt) r28() uint32       { return uint32(c.regs().sc_regs[28]) }

	_ Reg = iota
	R0
	R1
	R2
	R3
	R4
	R5
	R6
	R7
	R8
	R9
	R10
	R11
	R12
	R13
	R14
	R15
	R16
	R17
	R18
	R19
	R20
	R21
	R22
	R23
	R24
	R25
	R26
	R27
	R28
	R29
	R30
	R31
	F0
	F1
	F2
	F3
	F4
	F5
	F6
	F7
	F8
	F9
	F10
	F11
	F12
	F13
	F14
	F15
	F16
	F17
	F18
	F19
	F20

#else
#define ENDIAN_MOVE(off, ptr, dst, idx) \
	MOVD	$off,idx; \
	MOVWBR	(idx)(ptr), dst
#endif

#define M00 R18
#define M01 R19
#define M02 R20
#define M03 R24
#define M04 R25
#define M05 R26
#define M06 R27
#define M07 R28
#define M08 R29
#define M09 R21
#define M10 R11
#define M11 R8
#define M12 R7
#define M13 R12
#define M14 R23
#define M15 R10

	p("MOVW.P %d(R13), R15", lfp.stack+4) // load PC, pop frame (including the space pushed by sigctxt.pushCall)
	p("UNDEF")                            // shouldn't get here
}

func genARM64() {
	// Add integer registers R0-R26
	// R27 (REGTMP), R28 (g), R29 (FP), R30 (LR), R31 (SP) are special
	// and not saved here.
	var l = layout{sp: "RSP", stack: 8} // add slot to save PC of interrupted instruction
	for i := 0; i < 26; i += 2 {

		},

		// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
		// and sorts it to the very beginning of the block to prevent other
		// use of R26 (arm64.REGCTXT, the closure pointer)
		{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("R26")}}, zeroWidth: true},

		// LoweredGetCallerSP returns the SP of the caller of the current function. arg0=mem

	MOVD $128, R23
	MOVD $144, R24
	MOVD $160, R25
	MOVD $104, R26 // offset of sign+24(FP)

	LXVD2X (R16)(CPOOL), PH
	LXVD2X (R0)(CPOOL), PL

	LXVD2X (R17)(P2ptr), Y2L
	LXVD2X (R18)(P2ptr), Y2H
	XXPERMDI Y2H, Y2H, $2, Y2H
	XXPERMDI Y2L, Y2L, $2, Y2L

	// Equivalent of VLREPG sign+24(FP), SEL1
	LXVDSX   (R1)(R26), SEL1
	VSPLTISB $0, ZER
	VCMPEQUD SEL1, ZER, SEL1

	"R6",
	"R7",
	"R8",
	"R9",
	"R10",
	"R11",
	"R12",
	"R13",
	"R14",
	"R15",
	"R16",
	"R17",
	"R18",
	"R19",
	"R20",
	"R21",
	"g", // aka R22
	"R23",
	"R24",
	"R25",
	"R26",
	"R27",
	"R28",
	"R29",
	// R30 is REGTMP not used in regalloc
	"R31",

	"F0",
	"F1",
	"F2",
	"F3",
	"F4",
	"F5",
	"F6",
	"F7",
	"F8",
	"F9",
	"F10",
	"F11",
	"F12",

#define END	R5
#define TBL	R6
#define CNT	R8
#define LEN	R9
#define TEMP	R12

#define TBL_STRT R7 // Pointer to start of kcon table.

#define R_x000	R0
#define R_x010	R10
#define R_x020	R25
#define R_x030	R26
#define R_x040	R14
#define R_x050	R15
#define R_x060	R16
#define R_x070	R17
#define R_x080	R18
#define R_x090	R19
#define R_x0a0	R20
#define R_x0b0	R21
#define R_x0c0	R22
#define R_x0d0	R23

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

package org.gradle.integtests.tooling.r26

import groovy.transform.stc.ClosureParams
import groovy.transform.stc.SimpleType
import org.gradle.api.GradleException
import org.gradle.integtests.tooling.TestLauncherSpec