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src/cmd/asm/internal/asm/testdata/avx512enc/vpclmulqdq_avx512f.s
VPCLMULQDQ $127, X22, X21, X15 // 6233550044fe7f or 6233d50044fe7f VPCLMULQDQ $127, X7, X21, X15 // 6273550044ff7f or 6273d50044ff7f VPCLMULQDQ $127, X19, X21, X15 // 6233550044fb7f or 6233d50044fb7f VPCLMULQDQ $127, -17(BP)(SI*8), X21, X15 // 6273550044bcf5efffffff7f or 6273d50044bcf5efffffff7f VPCLMULQDQ $127, (R15), X21, X15 // 62535500443f7f or 6253d500443f7f
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue May 22 14:57:15 GMT 2018 - 8.2K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
CSRRC X0, CYCLE // ERROR "missing CSR name" CSRRC X0, CYCLE, (X10) // ERROR "needs an integer register output" CSRRC $-1, TIME, X15 // ERROR "immediate out of range 0 to 31" CSRRCI $32, TIME, X15 // ERROR "immediate out of range 0 to 31" CSRRCI $1, TIME, (X15) // ERROR "needs an integer register output" CSRRS (X10), CYCLE, X5 // ERROR "integer register or immediate expected for 1st operand"
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Wed Apr 01 04:17:57 GMT 2026 - 27.2K bytes - Click Count (0) -
lib/fips140/v1.26.0.zip
X14, X15, X16, X17, X10, X11) SHA256ROUND0(7, X11, X12, X13, X14, X15, X16, X17, X10) SHA256ROUND0(8, X10, X11, X12, X13, X14, X15, X16, X17) SHA256ROUND0(9, X17, X10, X11, X12, X13, X14, X15, X16) SHA256ROUND0(10, X16, X17, X10, X11, X12, X13, X14, X15) SHA256ROUND0(11, X15, X16, X17, X10, X11, X12, X13, X14) SHA256ROUND0(12, X14, X15, X16, X17, X10, X11, X12, X13) SHA256ROUND0(13, X13, X14, X15, X16, X17, X10, X11, X12) SHA256ROUND0(14, X12, X13, X14, X15, X16, X17, X10, X11) SHA256ROUND0(15, X11,...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Jan 08 17:58:32 GMT 2026 - 660.3K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
AUIPC $0, X10 // 17050000 AUIPC $0, X11 // 97050000 AUIPC $1, X10 // 17150000 AUIPC $-524288, X15 // 97070080 AUIPC $524287, X10 // 17f5ff7f LUI $0, X15 // b7070000 LUI $167, X15 // b7770a00 LUI $-524288, X15 // b7070080 LUI $524287, X15 // b7f7ff7f SLL X6, X5, X7 // b3936200 SLL X5, X6 // 33135300 SLL $1, X5, X6 // 13931200 SLL $1, X5 // 93921200
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Sat Apr 04 05:25:40 GMT 2026 - 74.2K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
VPGATHERQQ (BP)(Z20*2), K1, Z20 // ERROR "index and destination registers should be distinct" VPGATHERDQ (BP)(X2*2), K1, X2 // ERROR "index and destination registers should be distinct" VPGATHERDQ (BP)(X15*2), K1, Y15 // ERROR "index and destination registers should be distinct" VPGATHERDQ (BP)(Y20*2), K1, Z20 // ERROR "index and destination registers should be distinct" // Instructions without EVEX variant can't use High-16 registers.
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Wed Jun 14 00:03:57 GMT 2023 - 8.9K bytes - Click Count (0) -
lib/fips140/v1.0.0-c2097c7c.zip
X14, X15, X16, X17, X10, X11) SHA256ROUND0(7, X11, X12, X13, X14, X15, X16, X17, X10) SHA256ROUND0(8, X10, X11, X12, X13, X14, X15, X16, X17) SHA256ROUND0(9, X17, X10, X11, X12, X13, X14, X15, X16) SHA256ROUND0(10, X16, X17, X10, X11, X12, X13, X14, X15) SHA256ROUND0(11, X15, X16, X17, X10, X11, X12, X13, X14) SHA256ROUND0(12, X14, X15, X16, X17, X10, X11, X12, X13) SHA256ROUND0(13, X13, X14, X15, X16, X17, X10, X11, X12) SHA256ROUND0(14, X12, X13, X14, X15, X16, X17, X10, X11) SHA256ROUND0(15, X11,...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Sep 25 19:53:19 GMT 2025 - 642.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VPGATHERDQ 360(AX)(X2*4), K1, X1 // 62f2fd09904c902d VPGATHERDQ 640(BP)(X15*8), K3, X14 // 6232fd0b9074fd50 VPGATHERDQ 960(R10)(X25*2), K7, X24 // 6202fd0790444a78 VPGATHERDQ 1280(R10)(X1*4), K4, X0 // 62d2fd0c90848a00050000 VPGATHERDQ 360(AX)(X2*4), K1, Y1 // 62f2fd29904c902d VPGATHERDQ 640(BP)(X15*8), K3, Y14 // 6232fd2b9074fd50 VPGATHERDQ 960(R10)(X25*2), K7, Y24 // 6202fd2790444a78
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Feb 20 11:20:03 GMT 2025 - 57.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/operand_test.go
{"R9", "R9"}, {"g", "R14"}, {"SI", "SI"}, {"SP", "SP"}, {"X0", "X0"}, {"X1", "X1"}, {"X10", "X10"}, {"X11", "X11"}, {"X12", "X12"}, {"X13", "X13"}, {"X14", "X14"}, {"X15", "X15"}, {"X2", "X2"}, {"X3", "X3"}, {"X4", "X4"}, {"X5", "X5"}, {"X6", "X6"}, {"X7", "X7"}, {"X8", "X8"}, {"X9", "X9"}, {"_expand_key_128<>(SB)", "_expand_key_128<>(SB)"},Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue Aug 29 18:31:05 GMT 2023 - 23.9K bytes - Click Count (0) -
guava-tests/benchmark/com/google/common/base/EnumsBenchmark.java
} private enum MediumEnum { X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, X32,Created: Fri Apr 03 12:43:13 GMT 2026 - Last Modified: Thu Dec 19 18:03:30 GMT 2024 - 29.4K bytes - Click Count (0) -
android/guava-tests/benchmark/com/google/common/base/EnumsBenchmark.java
} private enum MediumEnum { X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, X32,Created: Fri Apr 03 12:43:13 GMT 2026 - Last Modified: Thu Dec 19 18:03:30 GMT 2024 - 29.4K bytes - Click Count (0)