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Results 61 - 70 of 70 for r23 (0.04 sec)
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src/cmd/internal/notsha256/sha256block_ppc64x.s
#define R_x030 R11 #define R_x040 R14 #define R_x050 R15 #define R_x060 R16 #define R_x070 R17 #define R_x080 R18 #define R_x090 R19 #define R_x0a0 R20 #define R_x0b0 R21 #define R_x0c0 R22 #define R_x0d0 R23 #define R_x0e0 R24 #define R_x0f0 R25 #define R_x100 R26 #define R_x110 R27 // V0-V7 are A-H // V8-V23 are used for the message schedule #define KI V24 #define FUNC V25 #define S0 V26
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 14.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
&& !config.noDuffDevice && logLargeCopy(v, s) => (DUFFCOPY [16 * (128 - s/8)] dst src mem) // 16 and 128 are magic constants. 16 is the number of bytes to encode: // MOVV (R1), R23 // ADDV $8, R1 // MOVV R23, (R2) // ADDV $8, R2 // and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy. // large or unaligned move uses a loop (Move [s] {t} dst src mem)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/obj9.go
// if(g->panic != nil && g->panic->argp == FP) g->panic->argp = bottom-of-frame // // MOVD g_panic(g), R22 // CMP R22, $0 // BEQ end // MOVD panic_argp(R22), R23 // ADD $(autosize+8), R1, R24 // CMP R23, R24 // BNE end // ADD $8, R1, R25 // MOVD R25, panic_argp(R22) // end: // NOP // // The NOP is needed to give the jumps somewhere to land.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 40.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
"R5", "R6", "R7", "R8", "R9", "R10", "R11", // REGCTXT for closures "R12", "R13", // REGTLS "R14", "R15", "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", "R24", "R25", "R26", "R27", "R28", "R29", "g", // REGG. Using name "g" and setting Config.hasGReg makes it "just happen". "R31", // REGTMP "F0", "F1", "F2", "F3", "F4",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64.rules
&& !config.noDuffDevice && logLargeCopy(v, s) => (DUFFCOPY [16 * (128 - s/8)] dst src mem) // 16 and 128 are magic constants. 16 is the number of bytes to encode: // MOVV (R1), R23 // ADDV $8, R1 // MOVV R23, (R2) // ADDV $8, R2 // and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy. // large or unaligned move uses a loop (Move [s] {t} dst src mem)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
"R5", "R6", "R7", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", "R16", "R17", "R18", // platform register, not used "R19", "R20", "R21", "R22", "R23", "R24", "R25", "R26", // R27 = REGTMP not used in regalloc "g", // aka R28 "R29", // frame pointer, not used "R30", // aka REGLINK "SP", // aka R31 "F0", "F1", "F2", "F3",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_ppc64le.s
MOVD in2+16(FP), P2ptr MOVD $p256mul<>+0x00(SB), CPOOL MOVD $16, R16 MOVD $32, R17 MOVD $48, R18 MOVD $64, R19 MOVD $80, R20 MOVD $96, R21 MOVD $112, R22 MOVD $128, R23 MOVD $144, R24 MOVD $160, R25 MOVD $104, R26 // offset of sign+24(FP) LXVD2X (R16)(CPOOL), PH LXVD2X (R0)(CPOOL), PL LXVD2X (R17)(P2ptr), Y2L LXVD2X (R18)(P2ptr), Y2H
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 56.5K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_arm64.s
#define t1 R12 #define t2 R13 #define t3 R14 #define const0 R15 #define const1 R16 #define hlp0 R17 #define hlp1 res_ptr #define x0 R19 #define x1 R20 #define x2 R21 #define x3 R22 #define y0 R23 #define y1 R24 #define y2 R25 #define y3 R26 #define const2 t2 #define const3 t3 DATA p256const0<>+0x00(SB)/8, $0x00000000ffffffff DATA p256const1<>+0x00(SB)/8, $0xffffffff00000001
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 29.7K bytes - Viewed (0) -
doc/asm.html
General purpose registers are named <code>R0</code> through <code>R31</code>, floating point registers are <code>F0</code> through <code>F31</code>. </p> <p> <code>R30</code> is reserved to point to <code>g</code>. <code>R23</code> is used as a temporary register. </p> <p> In a <code>TEXT</code> directive, the frame size <code>$-4</code> for MIPS or <code>$-8</code> for MIPS64 instructs the linker not to save <code>LR</code>. </p>
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (1) -
src/reflect/all_test.go
*R19 *R20 } type R14 R13 type R15 R13 type R16 R13 type R17 struct { *R21 *R22 *R23 *R24 } type R18 R17 type R19 R17 type R20 R17 type R21 struct { X int } type R22 R21 type R23 R21 type R24 R21 func TestEmbed(t *testing.T) { typ := TypeOf(R0{}) f, ok := typ.FieldByName("X") if ok {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 01:00:11 UTC 2024 - 218.8K bytes - Viewed (0)