return uint64(v) >> 16
}

func rshConst64Ux64Overflow8(v uint8) uint64 {
	// riscv64:"MOV\t\\$0,",-"SRL"
	return uint64(v) >> 8
}

func rshConst64x64(v int64) int64 {
	// ppc64x:"SRAD"
	// riscv64:"SRAI\t",-"OR",-"SLTIU"
	return v >> uint64(33)
}

func rshConst64x64Overflow32(v int32) int64 {
	// riscv64:"SRAIW",-"SLLI",-"SRAI\t"
	return int64(v) >> 32
}

	SLW	$4, R3, R6              // eb63000400df
	SLW	R2, R3, R6              // eb63200000df
	SLD	$4, R3, R6              // eb630004000d
	SLD	R2, R3, R6              // eb632000000d
	SRAD	$4, R5, R8              // eb850004000a
	SRAD	R3, R5, R8              // eb853000000a
	SRAW	$4, R5, R8              // eb85000400dc
	SRAW	R3, R5, R8              // eb85300000dc
	RLL	R1, R2, R3              // eb321000001d

	VRLQMI V1, V2, V3                       // 10611045
	VRLQNM V1, V2, V3                       // 10611145
	VSLDBI V1, V2, $3, V3                   // 106110d6
	VSLQ V1, V2, V3                         // 10611105
	VSRAQ V1, V2, V3                        // 10611305
	VSRDBI V1, V2, $3, V4                   // 108112d6
	VSRQ V1, V2, V3                         // 10611205
	VSTRIBL V1, V2                          // 1040080d

	// find leftmost one
	AFLOGR

	// population count
	APOPCNT

	// integer bitwise
	AAND
	AANDW
	AOR
	AORW
	AXOR
	AXORW
	ASLW
	ASLD
	ASRW
	ASRAW
	ASRD
	ASRAD
	ARLL
	ARLLG
	ARNSBG
	ARXSBG
	AROSBG
	ARNSBGT
	ARXSBGT
	AROSBGT
	ARISBG
	ARISBGN
	ARISBGZ
	ARISBGNZ
	ARISBHG
	ARISBLG
	ARISBHGZ
	ARISBLGZ

	"VPSHUFD",
	"VPSHUFHW",
	"VPSHUFLW",
	"VPSIGNB",
	"VPSIGND",
	"VPSIGNW",
	"VPSLLD",
	"VPSLLDQ",
	"VPSLLQ",
	"VPSLLVD",
	"VPSLLVQ",
	"VPSLLVW",
	"VPSLLW",
	"VPSRAD",
	"VPSRAQ",
	"VPSRAVD",
	"VPSRAVQ",
	"VPSRAVW",
	"VPSRAW",
	"VPSRLD",
	"VPSRLDQ",
	"VPSRLQ",
	"VPSRLVD",
	"VPSRLVQ",
	"VPSRLVW",
	"VPSRLW",
	"VPSUBB",

	// cond: shiftIsBounded(v)
	// result: (SRAD (MOVHreg x) y)
	for {
		x := v_0
		y := v_1
		if !(shiftIsBounded(v)) {
			break
		}
		v.reset(OpPPC64SRAD)
		v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64)
		v0.AddArg(x)
		v.AddArg2(v0, y)
		return true
	}
	// match: (Rsh16x16 <t> x y)

		v.AddArg2(x, y)
		return true
	}
	// match: (SRAD x (MOVWreg y))
	// result: (SRAD x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVWreg {
			break
		}
		y := v_1.Args[0]
		v.reset(OpS390XSRAD)
		v.AddArg2(x, y)
		return true
	}
	// match: (SRAD x (MOVHreg y))
	// result: (SRAD x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVHreg {

	VPSRAD X11, X9, X11                     // c44131e2db
	VPSRAD $7, X2, X9                       // c4e13172e207 or c5b172e207
	VPSRAD $7, X11, X9                      // c4c13172e307
	VPSRAD (BX), Y15, Y2                    // c4e105e213 or c585e213
	VPSRAD (R11), Y15, Y2                   // c4c105e213
	VPSRAD X2, Y15, Y2                      // c4e105e2d2 or c585e2d2

		{name: "FMSUB", argLength: 3, reg: fp31, asm: "FMSUB"},   // arg0*arg1 - arg2
		{name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS"}, // arg0*arg1 - arg2

		{name: "SRAD", argLength: 2, reg: gp21cxer, asm: "SRAD"}, // signed arg0 >> (arg1&127), 64 bit width (note: 127, not 63!)
		{name: "SRAW", argLength: 2, reg: gp21cxer, asm: "SRAW"}, // signed arg0 >> (arg1&63), 32 bit width

	CMP     $0,R6           // len == 0?
	BNE     start
	MOVW    R3,ret+40(FP)   // return crc
	RET

start:
	NOR     R3,R3,R7        // ^crc
	MOVWZ	R7,R7		// 32 bits
	CMP	R6,$16
	MOVD	R6,CTR
	BLT	short
	SRAD    $3,R6,R8        // 8 byte chunks
	MOVD    R8,CTR

loop:
	MOVWZ	0(R5),R8	// 0-3 bytes of p ?Endian?
	MOVWZ	4(R5),R9	// 4-7 bytes of p
	MOVD	R4,R10		// &tab[0]
	XOR	R7,R8,R7	// crc ^= byte[0:3]