polyMulStage3_AVX2
	VMOVDQA  CC3, tmpStoreAVX2
	VPSLLD   $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0
	VPSLLD   $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1
	VPSLLD   $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2
	VPSLLD   $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3
	VMOVDQA  tmpStoreAVX2, CC3
	polyMulReduceStage

	VPSRLD $126, (R8), K4, Z22                         // 62d14d4472107e
	VPSRLD $126, 15(DX)(BX*2), K4, Z22                 // 62f14d4472945a0f0000007e
	VPSRLD X17, X11, K7, X25                           // 6221250fd2c9
	VPSRLD 99(R15)(R15*4), X11, K7, X25                // 6201250fd28cbf63000000
	VPSRLD 15(DX), X11, K7, X25                        // 6261250fd28a0f000000
	VPSRLD X18, Y7, K2, Y21                            // 62a1452ad2ea

	RORXL    $2, a, T1;                   \ // T1 = (a >> 2)						// S0
	;                                     \
	XORL     g, y2;                       \ // y2 = CH = ((f^g)&e)^g				// CH
	VPSRLD   $7, XTMP1, XTMP2;            \
	XORL     T1, y1;                      \ // y1 = (a>>22) ^ (a>>13) ^ (a>>2)		// S0
	MOVL     a, T1;                       \ // T1 = a								// MAJB

#define PRECALC_18(REG) \
	VPXOR Y0, REG, REG \
	VPSLLDQ $12, REG, Y9

#define PRECALC_19(REG) \
	VPSLLD $1, REG, Y0 \
	VPSRLD $31, REG, REG

#define PRECALC_20(REG) \
	VPOR REG, Y0, Y0 \
	VPSLLD $2, Y9,  REG

#define PRECALC_21(REG) \
	VPSRLD $30, Y9, Y9 \
	VPXOR REG, Y0, Y0

#define PRECALC_23(REG,K_OFFSET,OFFSET) \
	VPXOR Y9, Y0, REG \
	VPADDD K_OFFSET(R8), REG, Y0 \

	"VPSLLD",
	"VPSLLDQ",
	"VPSLLQ",
	"VPSLLVD",
	"VPSLLVQ",
	"VPSLLVW",
	"VPSLLW",
	"VPSRAD",
	"VPSRAQ",
	"VPSRAVD",
	"VPSRAVQ",
	"VPSRAVW",
	"VPSRAW",
	"VPSRLD",
	"VPSRLDQ",
	"VPSRLQ",
	"VPSRLVD",
	"VPSRLVQ",
	"VPSRLVW",
	"VPSRLW",
	"VPSUBB",
	"VPSUBD",
	"VPSUBQ",
	"VPSUBSB",
	"VPSUBSW",
	"VPSUBUSB",
	"VPSUBUSW",

	VPSLLDQ $-1, X1, X2          // c5e973f9ff
	VPSLLDQ $-1, Y1, Y2          // c5ed73f9ff
	VPSLLQ $-1, X1, X2           // c5e973f1ff
	VPSLLQ $-1, Y1, Y2           // c5ed73f1ff
	VPSRLD $-1, X1, X2           // c5e972d1ff
	VPSRLD $-1, Y1, Y2           // c5ed72d1ff
	VPSRLDQ $-1, X1, X2          // c5e973d9ff
	VPSRLDQ $-1, Y1, Y2          // c5ed73d9ff
	VPSRLQ $-1, X1, X2           // c5e973d1ff

	VPSRAW $7, Y11, Y15                     // c4c10571e307
	VPSRLD (BX), X9, X2             // c4e131d213 or c5b1d213
	VPSRLD (R11), X9, X2            // c4c131d213
	VPSRLD X2, X9, X2               // c4e131d2d2 or c5b1d2d2
	VPSRLD X11, X9, X2              // c4c131d2d3
	VPSRLD (BX), X9, X11            // c46131d21b or c531d21b
	VPSRLD (R11), X9, X11           // c44131d21b
	VPSRLD X2, X9, X11              // c46131d2da or c531d2da