VPSRLDQ $121, 7(SI), Y0                            // 62f17d28739e0700000079 or 62f1fd28739e0700000079
	VPSRLDQ $13, Z21, Z12                              // 62b11d4873dd0d or 62b19d4873dd0d
	VPSRLDQ $13, Z9, Z12                               // 62d11d4873d90d or 62d19d4873d90d
	VPSRLDQ $13, 17(SP)(BP*1), Z12                     // 62f11d48739c2c110000000d or 62f19d48739c2c110000000d

	"VPSLLDQ",
	"VPSLLQ",
	"VPSLLVD",
	"VPSLLVQ",
	"VPSLLVW",
	"VPSLLW",
	"VPSRAD",
	"VPSRAQ",
	"VPSRAVD",
	"VPSRAVQ",
	"VPSRAVW",
	"VPSRAW",
	"VPSRLD",
	"VPSRLDQ",
	"VPSRLQ",
	"VPSRLVD",
	"VPSRLVQ",
	"VPSRLVW",
	"VPSRLW",
	"VPSUBB",
	"VPSUBD",
	"VPSUBQ",
	"VPSUBSB",
	"VPSUBSW",
	"VPSUBUSB",
	"VPSUBUSW",
	"VPSUBW",

	VPSLLQ $-1, X1, X2           // c5e973f1ff
	VPSLLQ $-1, Y1, Y2           // c5ed73f1ff
	VPSRLD $-1, X1, X2           // c5e972d1ff
	VPSRLD $-1, Y1, Y2           // c5ed72d1ff
	VPSRLDQ $-1, X1, X2          // c5e973d9ff
	VPSRLDQ $-1, Y1, Y2          // c5ed73d9ff
	VPSRLQ $-1, X1, X2           // c5e973d1ff
	VPSRLQ $-1, Y1, Y2           // c5ed73d1ff
	VPEXTRW $-1, X1, (AX)        // c4e3791508ff

	PRECALC_4(YREG,0x0) \
	PRECALC_7(OFFSET)


// Helper macros for PRECALC_16_31
#define PRECALC_16(REG_SUB_16,REG_SUB_12,REG_SUB_4,REG) \
	VPALIGNR $8, REG_SUB_16, REG_SUB_12, REG \  // w[i-14]
	VPSRLDQ $4, REG_SUB_4, Y0 // w[i-3]

#define PRECALC_17(REG_SUB_16,REG_SUB_8,REG) \
	VPXOR  REG_SUB_8, REG, REG \
	VPXOR  REG_SUB_16, Y0, Y0

#define PRECALC_18(REG) \
	VPXOR Y0, REG, REG \
	VPSLLDQ $12, REG, Y9

	VPSRLD $7, X2, X9               // c4e13172d207 or c5b172d207
	VPSRLD $7, X11, X9              // c4c13172d307
	VPSRLDQ $7, X2, X9              // c4e13173da07 or c5b173da07
	VPSRLDQ $7, X11, X9             // c4c13173db07
	VPSRLDQ $7, Y2, Y15             // c4e10573da07 or c58573da07
	VPSRLDQ $7, Y11, Y15            // c4c10573db07
	VPSRLQ (BX), X9, X2             // c4e131d313 or c5b1d313