// Code generated by stringer -i a.out.go -o anames.go -p ppc64; DO NOT EDIT.

package ppc64

import "cmd/internal/obj"

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADD",
	"ADDCC",
	"ADDIS",
	"ADDV",
	"ADDVCC",
	"ADDC",
	"ADDCCC",
	"ADDCV",
	"ADDCVCC",
	"ADDME",
	"ADDMECC",
	"ADDMEVCC",
	"ADDMEV",
	"ADDE",
	"ADDECC",
	"ADDEVCC",
	"ADDEV",
	"ADDZE",
	"ADDZECC",
	"ADDZEVCC",
	"ADDZEV",

	mov := "MOVW"
	movf := "MOVF"
	add := "ADD"
	sub := "SUB"
	r28 := "R28"
	regsize := 4
	softfloat := "GOMIPS_softfloat"
	if _64bit {
		mov = "MOVV"
		movf = "MOVD"
		add = "ADDV"
		sub = "SUBV"
		r28 = "RSB"
		regsize = 8
		softfloat = "GOMIPS64_softfloat"
	}

	// Add integer registers R1-R22, R24-R25, R28
	// R0 (zero), R23 (REGTMP), R29 (SP), R30 (g), R31 (LR) are special,

	LHBRX:     "MOVHBR",
	MCRF:      "MOVFL",
	XORI:      "XOR",
	ORI:       "OR",
	ANDICC:    "ANDCC",
	ANDC:      "ANDN",
	ANDCCC:    "ANDNCC",
	ADDEO:     "ADDEV",
	ADDEOCC:   "ADDEVCC",
	ADDO:      "ADDV",
	ADDOCC:    "ADDVCC",
	ADDMEO:    "ADDMEV",
	ADDMEOCC:  "ADDMEVCC",
	ADDCO:     "ADDCV",
	ADDCOCC:   "ADDCVCC",
	ADDZEO:    "ADDZEV",
	ADDZEOCC:  "ADDZEVCC",
	SUBFME:    "SUBME",

	MOVV	R3, R5
	MOVW	$1000000, R4
	DIVVU	R4, R3
	MOVV	LO, R3
	MOVV	R3, 8(R29)		// tv_sec
	MOVW	$1000, R4
	MULVU	R3, R4
	MOVV	LO, R4
	SUBVU	R4, R5
	MOVV	R5, 16(R29)		// tv_nsec

	ADDV	$8, R29, R4		// arg 1 - rqtp
	MOVV	$0, R5			// arg 2 - rmtp
	MOVV	$91, R2			// sys_nanosleep
	SYSCALL
	RET

TEXT runtime·getthrid(SB),NOSPLIT,$0-4
	MOVV	$299, R2		// sys_getthrid
	SYSCALL

	MOVV	R3, R5
	MOVW	$1000000, R4
	DIVVU	R4, R3
	MOVV	LO, R3
	MOVV	R3, 8(R29)
	MOVW	$1000, R4
	MULVU	R3, R4
	MOVV	LO, R4
	SUBVU	R4, R5
	MOVV	R5, 16(R29)

	// nanosleep(&ts, 0)
	ADDV	$8, R29, R4
	MOVW	$0, R5
	MOVV	$SYS_nanosleep, R2
	SYSCALL
	RET

TEXT runtime·gettid(SB),NOSPLIT,$0-4
	MOVV	$SYS_gettid, R2
	SYSCALL
	MOVW	R2, ret+0(FP)
	RET

var opstr = [...]string{
	ABS:       "ABS",
	ADC:       "ADC",
	ADCS:      "ADCS",
	ADD:       "ADD",
	ADDHN:     "ADDHN",
	ADDHN2:    "ADDHN2",
	ADDP:      "ADDP",
	ADDS:      "ADDS",
	ADDV:      "ADDV",
	ADR:       "ADR",
	ADRP:      "ADRP",
	AESD:      "AESD",
	AESE:      "AESE",
	AESIMC:    "AESIMC",
	AESMC:     "AESMC",
	AND:       "AND",
	ANDS:      "ANDS",
	ASR:       "ASR",

			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		v.reset(OpLOONG64MULV)
		v.AddArg2(x, y)
		return true
	}
	// match: (Select0 <t> (Add64carry x y c))
	// result: (ADDV (ADDV <t> x y) c)
	for {
		t := v.Type
		if v_0.Op != OpAdd64carry {
			break
		}
		c := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		v.reset(OpLOONG64ADDV)

		v0 := b.NewValue0(v.Pos, OpMIPS64MULVU, types.NewTuple(typ.UInt64, typ.UInt64))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
	// match: (Select0 <t> (Add64carry x y c))
	// result: (ADDV (ADDV <t> x y) c)
	for {
		t := v.Type
		if v_0.Op != OpAdd64carry {
			break
		}
		c := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		v.reset(OpMIPS64ADDV)

	ADDE R3, R4                     // 7c841914
	ADDECC R3, R4                   // 7c841915
	ADDEV R3, R4                    // 7c841d14
	ADDEVCC R3, R4                  // 7c841d15
	ADDV R3, R4                     // 7c841e14
	ADDVCC R3, R4                   // 7c841e15
	ADDCCC R3, R4, R5               // 7ca41815
	ADDCCC $65536, R4, R5           // 641f0001600000007cbf2015

{"Name":"ADDV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ADDV <V><d>, <Vn>.<T>","Code":"","Alias":""},