// in the usual way by the opcode itself. Asm must use AMRC for both instructions, so
// we return the opcode for MRC so that asm doesn't need to import obj/arm.
func ARMMRCOffset(op obj.As, cond string, x0, x1, x2, x3, x4, x5 int64) (offset int64, op0 obj.As, ok bool) {
	op1 := int64(0)
	if op == arm.AMRC {
		op1 = 1
	}
	bits, ok := ParseARMCondition(cond)
	if !ok {
		return
	}
	offset = (0xe << 24) | // opcode

	VAESDEC 99(R15)(R15*1), Z12, Z25                   // 62021d48de8c3f63000000 or 62029d48de8c3f63000000
	VAESDEC (DX), Z12, Z25                             // 62621d48de0a or 62629d48de0a
	VAESDECLAST X21, X5, X9                            // 62325508dfcd or 6232d508dfcd
	VAESDECLAST X21, X31, X9                           // 62320500dfcd or 62328500dfcd
	VAESDECLAST X1, X31, X9                            // 62720500dfc9 or 62728500dfc9

	VPCMPUW $79, X25, X5, K3, K1                       // 6293d50b3ec94f
	VPCMPUW $79, (CX), X5, K3, K1                      // 62f3d50b3e094f
	VPCMPUW $79, 99(R15), X5, K3, K1                   // 62d3d50b3e8f630000004f
	VPCMPUW $79, X25, X5, K3, K5                       // 6293d50b3ee94f
	VPCMPUW $79, (CX), X5, K3, K5                      // 62f3d50b3e294f
	VPCMPUW $79, 99(R15), X5, K3, K5                   // 62d3d50b3eaf630000004f

uint64(p384Uint1(x336))) var x377 uint64 var x378 uint64 x378, x377 = bits.Mul64(x5, arg2[5]) var x379 uint64 var x380 uint64 x380, x379 = bits.Mul64(x5, arg2[4]) var x381 uint64 var x382 uint64 x382, x381 = bits.Mul64(x5, arg2[3]) var x383 uint64 var x384 uint64 x384, x383 = bits.Mul64(x5, arg2[2]) var x385 uint64 var x386 uint64 x386, x385 = bits.Mul64(x5, arg2[1]) var x387 uint64 var x388 uint64 x388, x387 = bits.Mul64(x5, arg2[0]) var x389 uint64 var x390 uint64 x389, x390 = bits.Add64(x388, x385,...

// the validate function from being run and TestRISCVValidation will report missing
// errors.

TEXT validation(SB),$0
	SRLI	$1, X5, F1			// ERROR "expected integer register in rd position but got non-integer register F1"
	SRLI	$1, F1, X5			// ERROR "expected integer register in rs1 position but got non-integer register F1"

	//
	// "V" Standard Extension for Vector Operations, Version 1.0
	//

    }
    return retVal;
  }

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,
    X22,
    X23,

			x2 := int64(p.getRegister(prog, op, &a[2]))
			x3 := int64(p.getRegister(prog, op, &a[3]))
			x4 := int64(p.getRegister(prog, op, &a[4]))
			x5 := p.getConstant(prog, op, &a[5])
			// Cond is handled specially for this instruction.
			offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5)
			if !ok {
				p.errorf("unrecognized condition code .%q", cond)
			}
			prog.To.Offset = offset
			cond = ""

	XVMOVQ		X3, 3(R4)       // 830cc02c
	XVMOVQ		X4, 2040(R4)    // 84e0df2c
	XVMOVQ		X5, -2040(R4)   // 8520e02c
	XVMOVQ		X6, y+16(FP)    // 0660c02c
	XVMOVQ		X7, x+2030(FP)  // 07d8df2c
	XVMOVQ		(R4), X2        // 8200802c
	XVMOVQ		3(R4), X3       // 830c802c
	XVMOVQ		2044(R4), X4    // 84f09f2c
	XVMOVQ		-2044(R4), X5   // 8510a02c
	XVMOVQ		y+16(FP), X6    // 0660802c
	XVMOVQ		x+2030(FP), X7  // 07d89f2c