VAESDEC (SP), X0, X31                              // 62627d08de3c24 or 6262fd08de3c24
	VAESDEC X24, X7, X3                                // 62924508ded8 or 6292c508ded8
	VAESDEC X20, X7, X3                                // 62b24508dedc or 62b2c508dedc
	VAESDEC X24, X0, X3                                // 62927d08ded8 or 6292fd08ded8
	VAESDEC X20, X0, X3                                // 62b27d08dedc or 62b2fd08dedc

	VPSHLDW $65, X24, X7, K3, X3                       // 6293c50b70d841
	VPSHLDW $65, X20, X7, K3, X3                       // 62b3c50b70dc41
	VPSHLDW $65, X7, X7, K3, X3                        // 62f3c50b70df41
	VPSHLDW $65, 7(SI)(DI*8), X7, K3, X3               // 62f3c50b709cfe0700000041
	VPSHLDW $65, -15(R14), X7, K3, X3                  // 62d3c50b709ef1ffffff41
	VPSHLDW $65, X24, X0, K3, X3                       // 6293fd0b70d841

      int x0 = buf[bufLen - 1] & 0xff;
      int x1 = buf[bufLen - 2] & 0xff;
      int x2 = buf[bufLen - 3] & 0xff;
      int x3 = buf[bufLen / 2] & 0xff;
      buf[((x0 << 16) + (x1 << 8) + x2) % bufLen] ^= x3;
      buf[((x1 << 16) + (x2 << 8) + x3) % bufLen] ^= i % 256;
    }
    assertEquals(0x7a1d67c50ec7e167L, h);
  }

  private static long remix(long h) {
    h ^= h >>> 41;

	VPLZCNTD X3, K3, X17                               // 62e27d0b44cb
	VPLZCNTD X26, K3, X17                              // 62827d0b44ca
	VPLZCNTD X23, K3, X17                              // 62a27d0b44cf
	VPLZCNTD 15(DX)(BX*1), K3, X17                     // 62e27d0b448c1a0f000000
	VPLZCNTD -7(CX)(DX*2), K3, X17                     // 62e27d0b448c51f9ffffff
	VPLZCNTD X3, K3, X15                               // 62727d0b44fb

X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 ADDQ $0x20, CX enc128: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 32(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 48(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 64(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS...

	{"SI", "SI"},
	{"SP", "SP"},
	{"X0", "X0"},
	{"X1", "X1"},
	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},
	{"X15", "X15"},
	{"X2", "X2"},
	{"X3", "X3"},
	{"X4", "X4"},
	{"X5", "X5"},
	{"X6", "X6"},
	{"X7", "X7"},
	{"X8", "X8"},
	{"X9", "X9"},
	{"_expand_key_128<>(SB)", "_expand_key_128<>(SB)"},
	{"_seek<>(SB)", "_seek<>(SB)"},

	VPTESTNMW X7, X3, K1, K5                           // 62f2e60926ef
	VPTESTNMW (CX), X3, K1, K5                         // 62f2e6092629
	VPTESTNMW 99(R15), X3, K1, K5                      // 62d2e60926af63000000
	VPTESTNMW X7, X3, K1, K4                           // 62f2e60926e7
	VPTESTNMW (CX), X3, K1, K4                         // 62f2e6092621
	VPTESTNMW 99(R15), X3, K1, K4                      // 62d2e60926a763000000

// in the usual way by the opcode itself. Asm must use AMRC for both instructions, so
// we return the opcode for MRC so that asm doesn't need to import obj/arm.
func ARMMRCOffset(op obj.As, cond string, x0, x1, x2, x3, x4, x5 int64) (offset int64, op0 obj.As, ok bool) {
	op1 := int64(0)
	if op == arm.AMRC {
		op1 = 1
	}
	bits, ok := ParseARMCondition(cond)
	if !ok {
		return
	}
	offset = (0xe << 24) | // opcode

    eu6FSqdQgPCnXEqULl8FmTxSQeDNtGPPAUO6nIPcj2A781q0tHuu2guQOHXvgR1m
    0vdXcDazv/wor3ElhVsT/h5/WrQ8
    -----END CERTIFICATE-----
    """.trimIndent().decodeCertificatePem()

  // CN=Let's Encrypt Authority X3, O=Let's Encrypt, C=US
  val letsEncryptCertificateAuthority =
    """
    -----BEGIN CERTIFICATE-----
    MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/

    }
    return retVal;
  }

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,