return bits.RotateLeft8(n, s)
}

func RotateLeftVariable(n uint, m int) uint {
	// amd64:"ROLQ"
	// arm64:"ROR"
	// ppc64x:"ROTL"
	// s390x:"RLLG"
	// wasm:"I64Rotl"
	return bits.RotateLeft(n, m)
}

func RotateLeftVariable64(n uint64, m int) uint64 {
	// amd64:"ROLQ"
	// arm64:"ROR"
	// ppc64x:"ROTL"
	// s390x:"RLLG"
	// wasm:"I64Rotl"
	return bits.RotateLeft64(n, m)
}

	case sxtw:
		return "SXTW"

	case sxtx:
		return "SXTX"

	case lsl:
		return "LSL"

	case lsr:
		return "LSR"

	case asr:
		return "ASR"

	case ror:
		return "ROR"
	}
	return ""
}

type RegExtshiftAmount struct {
	reg       Reg
	extShift  ExtShift
	amount    uint8
	show_zero bool
}

func (RegExtshiftAmount) isArg() {}

	OR:        true,
	OUT:       true,
	POP:       true,
	POPA:      true,
	POPCNT:    true,
	PUSH:      true,
	PUSHA:     true,
	RCL:       true,
	RCR:       true,
	ROL:       true,
	ROR:       true,
	SAR:       true,
	SBB:       true,
	SHL:       true,
	SHLD:      true,
	SHR:       true,
	SHRD:      true,
	SUB:       true,
	TEST:      true,
	XADD:      true,
	XCHG:      true,

	ADDW $1864, R25, R6           <=>    add w6, w25, #0x748

Optionally-shifted registers are written as <Rm>{<shift><amount>}.
The <shift> can be <<(lsl), >>(lsr), ->(asr), @>(ror).

Examples:

	ADD R19>>30, R10, R24     <=>    add x24, x10, x19, lsr #30
	ADDW R26->24, R21, R15    <=>    add w15, w21, w26, asr #24

Extended registers are written as <Rm>{.<extend>{<<<amount>}}.

		{name: "ROLW", argLength: 2, reg: gp21, asm: "ROLW"},                  // rotate left least significant word of arg0 by (arg1 & 31), sign extended
		{name: "ROR", argLength: 2, reg: gp21, asm: "ROR"},                    // rotate right arg0 by (arg1 & 63)
		{name: "RORI", argLength: 1, reg: gp11, asm: "RORI", aux: "Int64"},    // rotate right arg0 by auxint, shift amount 0-63

	/*10550*/ uint16(xSetOp), uint16(ROR),
	/*10552*/ uint16(xReadIb),
	/*10553*/ uint16(xArgRM16),
	/*10554*/ uint16(xArgImm8u),
	/*10555*/ uint16(xMatch),
	/*10556*/ uint16(xSetOp), uint16(ROR),
	/*10558*/ uint16(xReadIb),
	/*10559*/ uint16(xArgRM32),
	/*10560*/ uint16(xArgImm8u),
	/*10561*/ uint16(xMatch),
	/*10562*/ uint16(xSetOp), uint16(ROR),
	/*10564*/ uint16(xReadIb),

	r := immr & levels
	esize = 1 << length
	if esize > datasize {
		return nil
	}
	welem = 1<<(s+1) - 1
	ror := (welem >> r) | (welem << (esize - r))
	ror &= ((1 << esize) - 1)
	wmask = 0
	for i = 0; i < datasize; i += esize {
		wmask = (wmask << esize) | ror
	}
	return Imm64{wmask, false}

	EXTRW $27, R4, R25, R19                    // 336f8413
	EXTR $17, R10, R29, R15                    // af47ca93
	ROR $14, R14, R15                          // cf39ce93
	RORW $28, R14, R15                         // cf718e13
	RORW R3, R12, R3                           // 832dc31a
	ROR R0, R23, R2                            // e22ec09a
	SBCW R4, R8, R24                           // 1801045a

				amount = fmt.Sprintf("%d", a.amount)
				return reg + extshift + amount

			case asr:
				extshift = "->"
				amount = fmt.Sprintf("%d", a.amount)
				return reg + extshift + amount
			case ror:
				extshift = "@>"
				amount = fmt.Sprintf("%d", a.amount)
				return reg + extshift + amount
			}
			if a.amount != 0 {
				amount = fmt.Sprintf("<<%d", a.amount)
			}
		}

(XOR (MOVDconst [val]) x) && is32Bit(val) => (XORI [val] x)
(ROL  x (MOVDconst [val])) => (RORI  [int64(int8(-val)&63)] x)
(ROLW x (MOVDconst [val])) => (RORIW [int64(int8(-val)&31)] x)
(ROR  x (MOVDconst [val])) => (RORI  [int64(val&63)] x)
(RORW x (MOVDconst [val])) => (RORIW [int64(val&31)] x)
(SLL  x (MOVDconst [val])) => (SLLI [int64(val&63)] x)
(SRL  x (MOVDconst [val])) => (SRLI [int64(val&63)] x)