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Results 1 - 9 of 9 for BFXIL (0.17 sec)
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test/codegen/bitfield.go
return (x << 24 >> 12) | (y & 0xfff0000000000fff) } // bfxil func bfxil1(x, y uint64) uint64 { // arm64:"BFXIL\t[$]5, R[0-9]+, [$]12",-"LSL",-"LSR",-"AND" return ((x >> 5) & 0xfff) | (y & 0xfffffffffffff000) } func bfxil2(x, y uint64) uint64 { // arm64:"BFXIL\t[$]12, R[0-9]+, [$]40",-"LSL",-"LSR",-"AND" return (x << 12 >> 24) | (y & 0xffffff0000000000) } // sbfiz
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 23 06:11:32 UTC 2022 - 9.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 18 01:40:37 UTC 2023 - 5.4K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/doc.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 07 00:21:42 UTC 2023 - 9.6K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go
rno := uint16(r) if rno <= uint16(WZR) { op += "W" } } args[1], args[2] = args[2], args[1] case STLXRB, STLXRH, STXRB, STXRH: args[1], args[2] = args[2], args[1] case BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX: if r, ok := inst.Args[0].(Reg); ok { rno := uint16(r) if rno <= uint16(WZR) { op += "W" } } args[1], args[2], args[3] = args[3], args[1], args[2]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 16 22:24:28 UTC 2022 - 17K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
// extract width bits of arg1 starting at bit lsb and insert at low end of result, copy other bits from arg0 {name: "BFXIL", argLength: 2, reg: gp21nog, asm: "BFXIL", aux: "ARM64BitField", resultInArg0: true},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
=> (BFI [armBFAuxInt(lc-rc, 64-lc)] x y) // bfxil (OR (UBFX [bfc] x) (ANDconst [ac] y)) && ac == ^(1<<uint(bfc.getARM64BFwidth())-1) => (BFXIL [bfc] y x) (ORshiftLL [sc] (UBFX [bfc] x) (SRLconst [sc] y)) && sc == bfc.getARM64BFwidth() => (BFXIL [bfc] y x) (ORshiftRL [rc] (ANDconst [ac] y) (SLLconst [lc] x)) && lc < rc && ac == ^((1<<uint(64-rc)-1)) => (BFXIL [armBFAuxInt(rc-lc, 64-rc)] y x) // FP simplification
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
JMP -1(PC) // ffffff17 BFIW $16, R20, $6, R0 // 80161033 BFI $27, R21, $21, R25 // b95265b3 BFXILW $3, R27, $23, R14 // 6e670333 BFXIL $26, R8, $16, R20 // 14a55ab3 BICW R7@>15, R5, R16 // b03ce70a BIC R12@>13, R12, R19 // 9335ec8a BICSW R25->20, R3, R20 // 7450b96a
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
v.AddArg2(y, x) return true } break } // match: (OR (UBFX [bfc] x) (ANDconst [ac] y)) // cond: ac == ^(1<<uint(bfc.getARM64BFwidth())-1) // result: (BFXIL [bfc] y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64UBFX { continue } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BFXIL", auxType: auxARM64BitField, argLen: 2, resultInArg0: true, asm: arm64.ABFXIL, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)