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Results 11 - 20 of 22 for SUBW (0.05 sec)

  1. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	STXRH R12, (R3), R8                        // 6c7c0848
    	SUBW R20.UXTW<<2, R23, R19                 // f34a344b
    	SUB R5.SXTW<<2, R1, R26                    // 3ac825cb
    	SUB $(1923<<12), R4, R27                   // SUB $7876608, R4, R27         // 9b0c5ed1
    	SUBW $(1923<<12), R4, R27                  // SUBW $7876608, R4, R27        // 9b0c5e51
    	SUBW R12<<29, R7, R8                       // e8740c4b
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/S390X.rules

    (ADDW x (MOVDconst [c])) => (ADDWconst [int32(c)] x)
    
    (SUB x (MOVDconst [c])) && is32Bit(c) => (SUBconst x [int32(c)])
    (SUB (MOVDconst [c]) x) && is32Bit(c) => (NEG (SUBconst <v.Type> x [int32(c)]))
    (SUBW x (MOVDconst [c])) => (SUBWconst x [int32(c)])
    (SUBW (MOVDconst [c]) x) => (NEGW (SUBWconst <v.Type> x [int32(c)]))
    
    (MULLD x (MOVDconst [c])) && is32Bit(c) => (MULLDconst [int32(c)] x)
    (MULLW x (MOVDconst [c])) => (MULLWconst [int32(c)] x)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (SUB <t> (MOVDconst [val]) y) && is32Bit(-val) => (NEG (ADDI <t> [-val] y))
    
    // Subtraction of zero.
    (SUB  x (MOVDconst [0])) => x
    (SUBW x (MOVDconst [0])) => (ADDIW [0] x)
    
    // Subtraction from zero.
    (SUB  (MOVDconst [0]) x) => (NEG x)
    (SUBW (MOVDconst [0]) x) => (NEGW x)
    
    // Fold negation into subtraction.
    (NEG (SUB x y)) => (SUB y x)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/S390XOps.go

    		{name: "SUB", argLength: 2, reg: gp21, asm: "SUB", clobberFlags: true},                                                                                       // arg0 - arg1
    		{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW", clobberFlags: true},                                                                                     // arg0 - arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 52.5K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"},                  // -arg0 of 32 bits, sign extended to 64 bits
    		{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"},                    // arg0 - arg1
    		{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW"},                  // 32 low bits of arg 0 - 32 low bits of arg 1, sign extended to 64 bits
    
    		// M extension. H means high (i.e., it returns the top bits of
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/x86/anames.go

    	"STI",
    	"STMXCSR",
    	"STOSB",
    	"STOSL",
    	"STOSQ",
    	"STOSW",
    	"STRL",
    	"STRQ",
    	"STRW",
    	"SUBB",
    	"SUBL",
    	"SUBPD",
    	"SUBPS",
    	"SUBQ",
    	"SUBSD",
    	"SUBSS",
    	"SUBW",
    	"SWAPGS",
    	"SYSCALL",
    	"SYSENTER",
    	"SYSENTER64",
    	"SYSEXIT",
    	"SYSEXIT64",
    	"SYSRET",
    	"TESTB",
    	"TESTL",
    	"TESTQ",
    	"TESTW",
    	"TPAUSE",
    	"TZCNTL",
    	"TZCNTQ",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 19.1K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/arm64error.s

    	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUBS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 37.8K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/arm64.s

    	ADDSW	R19.UXTW, R14, R17              // d141332b
    	ADDS	R12.SXTX, R3, R1                // 61e02cab
    	SUB	R19.UXTH<<4, R2, R21            // 553033cb
    	SUBW	R1.UXTX<<1, R3, R2              // 6264214b
    	SUBS	R3.UXTX, R8, R9                 // 096123eb
    	SUBSW	R17.UXTH, R15, R21              // f521316b
    	SUBW	ZR<<14, R19, R13                // 6d3a1f4b
    	CMP	R2.SXTH, R13                    // bfa122eb
    	CMN	R1.SXTX<<2, R10                 // 5fe921ab
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 94.9K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewriteS390X.go

    	v_0 := v.Args[0]
    	b := v.Block
    	// match: (SUBW x (MOVDconst [c]))
    	// result: (SUBWconst x [int32(c)])
    	for {
    		x := v_0
    		if v_1.Op != OpS390XMOVDconst {
    			break
    		}
    		c := auxIntToInt64(v_1.AuxInt)
    		v.reset(OpS390XSUBWconst)
    		v.AuxInt = int32ToAuxInt(int32(c))
    		v.AddArg(x)
    		return true
    	}
    	// match: (SUBW (MOVDconst [c]) x)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 395.1K bytes
    - Viewed (0)
  10. src/runtime/asm_arm64.s

    	VEOR	V0.B16, V2.B16, V0.B16
    	VEOR	V4.B16, V6.B16, V4.B16
    	VEOR	V4.B16, V0.B16, V0.B16
    
    	VMOV	V0.D[0], R0
    	RET
    
    TEXT runtime·procyield(SB),NOSPLIT,$0-0
    	MOVWU	cycles+0(FP), R0
    again:
    	YIELD
    	SUBW	$1, R0
    	CBNZ	R0, again
    	RET
    
    // Save state of caller into g->sched,
    // but using fake PC from systemstack_switch.
    // Must only be called from functions with no locals ($0)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat May 11 20:38:24 UTC 2024
    - 43.4K bytes
    - Viewed (0)
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