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Results 1 - 10 of 45 for divweu (0.2 sec)

  1. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

    	DCFFIXCC:       "dcffix.",
    	DIVDE:          "divde",
    	DIVDECC:        "divde.",
    	DIVDEO:         "divdeo",
    	DIVDEOCC:       "divdeo.",
    	DIVDEU:         "divdeu",
    	DIVDEUCC:       "divdeu.",
    	DIVDEUO:        "divdeuo",
    	DIVDEUOCC:      "divdeuo.",
    	DIVWE:          "divwe",
    	DIVWECC:        "divwe.",
    	DIVWEO:         "divweo",
    	DIVWEOCC:       "divweo.",
    	DIVWEU:         "divweu",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 334.7K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/ppc64/anames.go

    	"CMP",
    	"CMPU",
    	"CMPEQB",
    	"CNTLZW",
    	"CNTLZWCC",
    	"CRAND",
    	"CRANDN",
    	"CREQV",
    	"CRNAND",
    	"CRNOR",
    	"CROR",
    	"CRORN",
    	"CRXOR",
    	"DIVW",
    	"DIVWCC",
    	"DIVWVCC",
    	"DIVWV",
    	"DIVWU",
    	"DIVWUCC",
    	"DIVWUVCC",
    	"DIVWUV",
    	"MODUD",
    	"MODUW",
    	"MODSD",
    	"MODSW",
    	"EQV",
    	"EQVCC",
    	"EXTSB",
    	"EXTSBCC",
    	"EXTSH",
    	"EXTSHCC",
    	"FABS",
    	"FABSCC",
    	"FADD",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/generic.rules

    (Div64  (Const64 [c])  (Const64 [d])) && d != 0 => (Const64 [c/d])
    (Div8u  (Const8  [c])  (Const8  [d])) && d != 0 => (Const8  [int8(uint8(c)/uint8(d))])
    (Div16u (Const16 [c])  (Const16 [d])) && d != 0 => (Const16 [int16(uint16(c)/uint16(d))])
    (Div32u (Const32 [c])  (Const32 [d])) && d != 0 => (Const32 [int32(uint32(c)/uint32(d))])
    (Div64u (Const64 [c])  (Const64 [d])) && d != 0 => (Const64 [int64(uint64(c)/uint64(d))])
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 16 22:21:05 UTC 2024
    - 135.3K bytes
    - Viewed (0)
  4. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go

    	case ADD, ADDC, ADDE, ADDCC, ADDCCC:
    		return true
    	case MULLW, MULLWCC, MULHW, MULHWCC, MULLD, MULLDCC, MULHD, MULHDCC, MULLWO, MULLWOCC, MULHWU, MULHWUCC, MULLDO, MULLDOCC:
    		return true
    	case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC:
    		return true
    	case MODUD, MODSD, MODUW, MODSW:
    		return true
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 10.9K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/Wasm.rules

    (Div16 [false] x y) => (I64DivS (SignExt16to64 x) (SignExt16to64 y))
    (Div8          x y) => (I64DivS (SignExt8to64 x) (SignExt8to64 y))
    (Div64u ...) => (I64DivU ...)
    (Div32u x y) => (I64DivU (ZeroExt32to64 x) (ZeroExt32to64 y))
    (Div16u x y) => (I64DivU (ZeroExt16to64 x) (ZeroExt16to64 y))
    (Div8u  x y) => (I64DivU (ZeroExt8to64 x) (ZeroExt8to64 y))
    (Div(64|32)F ...) => (F(64|32)Div ...)
    
    (Mod64 [false] x y) => (I64RemS x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 17 03:56:57 UTC 2023
    - 16.9K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Select1 (Mul64uhilo x y)) => (MULLD x y)
    
    (Div64 [false] x y) => (DIVD x y)
    (Div64u ...) => (DIVDU ...)
    (Div32 [false] x y) => (DIVW x y)
    (Div32u ...) => (DIVWU ...)
    (Div16 [false]  x y) => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
    (Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
    (Div8 x y) => (DIVW  (SignExt8to32 x) (SignExt8to32 y))
    (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/S390X.rules

    (Div64F ...) => (FDIV ...)
    
    (Div64 x y) => (DIVD x y)
    (Div64u ...) => (DIVDU ...)
    // DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor,
    // so a sign/zero extension of the dividend is required.
    (Div32  x y) => (DIVW  (MOVWreg x) y)
    (Div32u x y) => (DIVWU (MOVWZreg x) y)
    (Div16  x y) => (DIVW  (MOVHreg x) (MOVHreg y))
    (Div16u x y) => (DIVWU (MOVHZreg x) (MOVHZreg y))
    (Div8   x y) => (DIVW  (MOVBreg x) (MOVBreg y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/ppc64/a.out.go

    	ACMP
    	ACMPU
    	ACMPEQB
    	ACNTLZW
    	ACNTLZWCC
    	ACRAND
    	ACRANDN
    	ACREQV
    	ACRNAND
    	ACRNOR
    	ACROR
    	ACRORN
    	ACRXOR
    	ADIVW
    	ADIVWCC
    	ADIVWVCC
    	ADIVWV
    	ADIVWU
    	ADIVWUCC
    	ADIVWUVCC
    	ADIVWUV
    	AMODUD
    	AMODUW
    	AMODSD
    	AMODSW
    	AEQV
    	AEQVCC
    	AEXTSB
    	AEXTSBCC
    	AEXTSH
    	AEXTSHCC
    	AFABS
    	AFABSCC
    	AFADD
    	AFADDCC
    	AFADDS
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 16K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/s390x/anames.go

    package s390x
    
    import "cmd/internal/obj"
    
    var Anames = []string{
    	obj.A_ARCHSPECIFIC: "ADD",
    	"ADDC",
    	"ADDE",
    	"ADDW",
    	"DIVW",
    	"DIVWU",
    	"DIVD",
    	"DIVDU",
    	"MODW",
    	"MODWU",
    	"MODD",
    	"MODDU",
    	"MULLW",
    	"MULLD",
    	"MULHD",
    	"MULHDU",
    	"MLGR",
    	"SUB",
    	"SUBC",
    	"SUBV",
    	"SUBE",
    	"SUBW",
    	"NEG",
    	"NEGW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Sep 05 16:41:03 UTC 2023
    - 7.1K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/ppc64.s

    	DIVD R3, R4, R5                 // 7ca41bd2
    	DIVW R3, R4                     // 7c841bd6
    	DIVW R3, R4, R5                 // 7ca41bd6
    	DIVDCC R3,R4, R5                // 7ca41bd3
    	DIVWCC R3,R4, R5                // 7ca41bd7
    	DIVDU R3, R4, R5                // 7ca41b92
    	DIVWU R3, R4, R5                // 7ca41b96
    	DIVDV R3, R4, R5                // 7ca41fd2
    	DIVWV R3, R4, R5                // 7ca41fd6
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
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