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Results 1 - 10 of 107 for divr (0.07 sec)

  1. test/codegen/arithmetic.go

    		d += e
    	}
    	return d, e
    }
    
    func NoFix32A(divr int32) (int32, int32) {
    	var d int32 = 42
    	var e int32 = 84
    	if divr > 5 {
    		// amd64:-"JMP"
    		// 386:-"JMP"
    		d /= divr
    		// amd64:-"JMP"
    		// 386:-"JMP"
    		e %= divr
    		d += e
    	}
    	return d, e
    }
    
    func NoFix32B(divd int32) (int32, int32) {
    	var d int32
    	var e int32
    	var divr int32 = -1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 15:28:00 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/prove.go

    			// TODO: add other architectures?
    			if b.Func.Config.arch != "386" && b.Func.Config.arch != "amd64" {
    				break
    			}
    			divr := v.Args[1]
    			divrLim, divrLimok := ft.limits[divr.ID]
    			divd := v.Args[0]
    			divdLim, divdLimok := ft.limits[divd.ID]
    			if (divrLimok && (divrLim.max < -1 || divrLim.min > -1)) ||
    				(divdLimok && divdLim.min > mostNegativeDividend[v.Op]) {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:30:21 UTC 2024
    - 48.9K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/mips/anames.go

    	"BLTZAL",
    	"BNE",
    	"BREAK",
    	"CLO",
    	"CLZ",
    	"CMOVF",
    	"CMOVN",
    	"CMOVT",
    	"CMOVZ",
    	"CMPEQD",
    	"CMPEQF",
    	"CMPGED",
    	"CMPGEF",
    	"CMPGTD",
    	"CMPGTF",
    	"DIV",
    	"DIVD",
    	"DIVF",
    	"DIVU",
    	"DIVW",
    	"GOK",
    	"LL",
    	"LLV",
    	"LUI",
    	"MADD",
    	"MOVB",
    	"MOVBU",
    	"MOVD",
    	"MOVDF",
    	"MOVDW",
    	"MOVF",
    	"MOVFD",
    	"MOVFW",
    	"MOVH",
    	"MOVHU",
    	"MOVW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 1.4K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/loong64/anames.go

    	"CMPEQF",
    	"CMPGED",
    	"CMPGEF",
    	"CMPGTD",
    	"CMPGTF",
    	"LU12IW",
    	"LU32ID",
    	"LU52ID",
    	"PCALAU12I",
    	"PCADDU12I",
    	"JIRL",
    	"BGE",
    	"BLT",
    	"BLTU",
    	"BGEU",
    	"DIV",
    	"DIVD",
    	"DIVF",
    	"DIVU",
    	"DIVW",
    	"LL",
    	"LLV",
    	"LUI",
    	"MOVB",
    	"MOVBU",
    	"MOVD",
    	"MOVDF",
    	"MOVDW",
    	"MOVF",
    	"MOVFD",
    	"MOVFW",
    	"MOVH",
    	"MOVHU",
    	"MOVW",
    	"MOVWD",
    	"MOVWF",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/armv6.s

    	FNMULAF F5, F6, F7    // 457a96ee
    	FNMULAD F5, F6, F7    // 457b96ee
    	FNMULSF F5, F6, F7    // 057a96ee
    	FNMULSD F5, F6, F7    // 057b96ee
    	DIVF	F0, F1, F2    // 002a81ee
    	DIVD.EQ	F3, F4, F5    // 035b840e
    	DIVF.NE	F0, F2        // 002a821e
    	DIVD	F3, F5        // 035b85ee
    	NEGF	F0, F1        // 401ab1ee
    	NEGD	F4, F5        // 445bb1ee
    	ABSF	F0, F1        // c01ab0ee
    	ABSD	F4, F5        // c45bb0ee
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Dec 21 16:30:51 UTC 2017
    - 4.6K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/arm/anames.go

    	"NMULSD",
    	"FMULAF",
    	"FMULAD",
    	"FNMULAF",
    	"FNMULAD",
    	"FMULSF",
    	"FMULSD",
    	"FNMULSF",
    	"FNMULSD",
    	"DIVF",
    	"DIVD",
    	"SQRTF",
    	"SQRTD",
    	"ABSF",
    	"ABSD",
    	"NEGF",
    	"NEGD",
    	"SRL",
    	"SRA",
    	"SLL",
    	"MULU",
    	"DIVU",
    	"MUL",
    	"MMUL",
    	"DIV",
    	"MOD",
    	"MODU",
    	"DIVHW",
    	"DIVUHW",
    	"MOVB",
    	"MOVBS",
    	"MOVBU",
    	"MOVH",
    	"MOVHS",
    	"MOVHU",
    	"MOVW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 16 15:58:33 UTC 2019
    - 1.4K bytes
    - Viewed (0)
  7. tensorflow/compiler/jit/deadness_analysis_test.cc

      DependentInductionVar div0 =
          CreateDependentLoopInvariantValue(root, "div0", "loop", iv.loop_cond, 0);
      DependentInductionVar div1 =
          CreateDependentLoopInvariantValue(root, "div1", "loop", iv.loop_cond, 0);
      FixupSourceAndSinkEdges(root.graph());
      TF_ASSERT_OK(root.graph()->UpdateEdge(div1.induction_var.node(), 0,
                                            div0.latch.output_true.node(), 0));
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Feb 22 06:59:07 UTC 2024
    - 51.6K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/MIPSOps.go

    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    
    		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                // arg0 & arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 24K bytes
    - Viewed (0)
  9. apache-maven/src/assembly/dir.xml

    <assembly xmlns="http://maven.apache.org/ASSEMBLY/2.1.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
        xsi:schemaLocation="http://maven.apache.org/ASSEMBLY/2.1.0 http://maven.apache.org/xsd/assembly-2.1.0.xsd">
      <id>dir</id>
      <formats>
        <format>dir</format>
      </formats>
      <includeBaseDirectory>false</includeBaseDirectory>
      <componentDescriptors>
        <componentDescriptor>src/assembly/component.xml</componentDescriptor>
      </componentDescriptors>
    Registered: Wed Jun 12 09:55:16 UTC 2024
    - Last Modified: Wed Apr 27 13:14:24 UTC 2022
    - 1.2K bytes
    - Viewed (0)
  10. src/os/dir.go

    	slices.SortFunc(dirs, func(a, b DirEntry) int {
    		return bytealg.CompareString(a.Name(), b.Name())
    	})
    	return dirs, err
    }
    
    // CopyFS copies the file system fsys into the directory dir,
    // creating dir if necessary.
    //
    // Newly created directories and files have their default modes
    // where any bits from the file in fsys that are not part of the
    // standard read, write, and execute permissions will be zeroed
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 01:00:11 UTC 2024
    - 6.1K bytes
    - Viewed (0)
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