XORQ R15, R15
	RET
TEXT ·a5(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	XORL R15, R15
	RET
TEXT ·a6(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	POPQ R15
	PUSHQ R15
	RET
TEXT ·a7(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	MOVQ R15, AX // ERROR "when dynamic linking, R15 is clobbered by a global variable access and is used here"
	RET
TEXT ·a8(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0

	VGATHERDPD 360(R15)(Y30*2), K6, Z20 // 6282fd469264772d
	VGATHERDPD 640(R15)(Y20*2), K6, Z10 // 6252fd4692546750
	VGATHERDPD 960(R15)(Y10*2), K6, Z20 // 6282fd4e92645778
	VGATHERDPD 1280(R15)(Y0*2), K6, Z10 // 6252fd4e92944700050000
	VGATHERDPS 360(R15)(X30*2), K6, X20 // 62827d069264775a
	VGATHERDPS 640(R15)(X20*2), K6, X10 // 62527d0692946780020000
	VGATHERDPS 960(R15)(X10*2), K6, X20 // 62827d0e92a457c0030000

	MOVD	(R15), R1             // e310f0000004
	MOVW	(R15), R2             // e320f0000014
	MOVH	(R15), R3             // e330f0000015
	MOVB	(R15), R4             // e340f0000077
	MOVWZ	(R15), R5             // e350f0000016
	MOVHZ	(R15), R6             // e360f0000091
	MOVBZ	(R15), R7             // e370f0000090
	MOVDBR	(R15), R8             // e380f000000f
	MOVWBR	(R15), R9             // e390f000001e

	CLREX $0                                   // 5f3003d5
	CLSW R15, R6                               // e615c05a
	CLS R15, ZR                                // ff15c0da
	CLZW R1, R14                               // 2e10c05a
	CLZ R21, R9                                // a912c0da
	CMNW R21.UXTB<<4, R15                      // ff11352b
	CMN R0.UXTW<<4, R16                        // 1f5220ab

	{"R11", "R11"},
	{"R12", "R12"},
	{"R13", "R13"},
	{"R14", "R14"},
	{"R15", "R15"},
	{"R1<<2(R3)", "R1<<2(R3)"},
	{"R(1)<<2(R(3))", "R1<<2(R3)"},
	{"R2", "R2"},
	{"R3", "R3"},
	{"R4", "R4"},
	{"R(4)", "R4"},
	{"R5", "R5"},
	{"R6", "R6"},
	{"R7", "R7"},
	{"R8", "R8"},
	{"[R0,R1,g,R15]", "[R0,R1,g,R15]"},
	{"[R0-R7]", "[R0,R1,R2,R3,R4,R5,R6,R7]"},
	{"[R(0)-R(7)]", "[R0,R1,R2,R3,R4,R5,R6,R7]"},

	VLD1R.P	(R15)(R1), [V15.H4]                             // efc5c10d
	VLD2R	(R15), [V15.H4, V16.H4]                         // efc5600d
	VLD2R.P	16(R0), [V0.D2, V1.D2]                          // 00ccff4d
	VLD2R.P	(R0)(R5), [V31.D1, V0.D1]                       // 1fcce50d
	VLD3R	(RSP), [V31.S2, V0.S2, V1.S2]                   // ffeb400d
	VLD3R.P	6(R15), [V15.H4, V16.H4, V17.H4]                // efe5df0d

//	LMOVB rreg ',' addr
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	MOVB	R1, foo<>+3(SB)
	MOVB	R5, -18(R4)	// a085ffee
	MOVB	R10, 9(R13)	// a1aa0009
	MOVB	R15, (R13)	// a1af0000
	MOVBU	R5, -18(R4)	// a085ffee
	MOVBU	R10, 9(R13)	// a1aa0009
	MOVBU	R15, (R13)	// a1af0000

//
// store floats
//
//	LMOVW freg ',' addr
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	MOVD	F1, foo<>+3(SB)

<code>&gt;&gt;</code> (logical right shift), and
<code>@&gt;</code> (rotate right).

</li>

<li>
<code>[R0,g,R12-R15]</code>: For multi-register instructions, the set comprising
<code>R0</code>, <code>g</code>, and <code>R12</code> through <code>R15</code> inclusive.
</li>

<li>
<code>(R5, R6)</code>: Destination register pair.
</li>

</ul>

<h3 id="arm64">ARM64</h3>

	}
	if name[0] != 'R' {
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	r, ok := p.registerReference(name)
	if !ok {
		return 0
	}
	reg := r - p.arch.Register["R0"]
	if reg < 0 {
		// Could happen for an architecture having other registers prefixed by R
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	return uint16(reg)
}

func archS390x() *Arch {
	register := make(map[string]int16)
	// Create maps for easy lookup of instruction names etc.
	// Note that there is no list of names as there is for x86.
	for i := s390x.REG_R0; i <= s390x.REG_R15; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	for i := s390x.REG_F0; i <= s390x.REG_F15; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	for i := s390x.REG_V0; i <= s390x.REG_V31; i++ {