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Results 1 - 10 of 20 for vsraw (0.05 sec)

  1. src/cmd/internal/obj/ppc64/anames.go

    	"VR",
    	"VRLB",
    	"VRLH",
    	"VRLW",
    	"VRLD",
    	"VS",
    	"VSLB",
    	"VSLH",
    	"VSLW",
    	"VSL",
    	"VSLO",
    	"VSRB",
    	"VSRH",
    	"VSRW",
    	"VSR",
    	"VSRO",
    	"VSLD",
    	"VSRD",
    	"VSA",
    	"VSRAB",
    	"VSRAH",
    	"VSRAW",
    	"VSRAD",
    	"VSOI",
    	"VSLDOI",
    	"VCLZ",
    	"VCLZB",
    	"VCLZH",
    	"VCLZW",
    	"VCLZD",
    	"VPOPCNT",
    	"VPOPCNTB",
    	"VPOPCNTH",
    	"VPOPCNTW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/ppc64.s

    	VSRH V1, V2, V3                 // 10611244
    	VSRW V1, V2, V3                 // 10611284
    	VSRD V1, V2, V3                 // 106116c4
    	VSR V1, V2, V3                  // 106112c4
    	VSRO V1, V2, V3                 // 1061144c
    	VSLD V1, V2, V3                 // 106115c4
    	VSRAB V1, V2, V3                // 10611304
    	VSRAH V1, V2, V3                // 10611344
    	VSRAW V1, V2, V3                // 10611384
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/ppc64/asm9.go

    			opset(AVSRH, r0)
    			opset(AVSRW, r0)
    			opset(AVSR, r0)
    			opset(AVSRO, r0)
    			opset(AVSLD, r0)
    			opset(AVSRD, r0)
    
    		case AVSA: /* vsrab, vsrah, vsraw, vsrad */
    			opset(AVSRAB, r0)
    			opset(AVSRAH, r0)
    			opset(AVSRAW, r0)
    			opset(AVSRAD, r0)
    
    		case AVSOI: /* vsldoi */
    			opset(AVSLDOI, r0)
    
    		case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */
    			opset(AVCLZB, r0)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 13:55:28 UTC 2024
    - 156.1K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/ppc64/a.out.go

    	ANEGV
    	ANOR
    	ANORCC
    	AOR
    	AORCC
    	AORN
    	AORNCC
    	AORIS
    	AREM
    	AREMU
    	ARFI
    	ARLWMI
    	ARLWMICC
    	ARLWNM
    	ARLWNMCC
    	ACLRLSLWI
    	ASLW
    	ASLWCC
    	ASRW
    	ASRAW
    	ASRAWCC
    	ASRWCC
    	ASTBCCC
    	ASTHCCC
    	ASTSW
    	ASTWCCC
    	ASUB
    	ASUBCC
    	ASUBVCC
    	ASUBC
    	ASUBCCC
    	ASUBCV
    	ASUBCVCC
    	ASUBME
    	ASUBMECC
    	ASUBMEVCC
    	ASUBMEV
    	ASUBV
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 16K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/riscv/anames.go

    	"LWU",
    	"LH",
    	"LHU",
    	"LB",
    	"LBU",
    	"SW",
    	"SH",
    	"SB",
    	"FENCE",
    	"FENCETSO",
    	"PAUSE",
    	"ADDIW",
    	"SLLIW",
    	"SRLIW",
    	"SRAIW",
    	"ADDW",
    	"SLLW",
    	"SRLW",
    	"SUBW",
    	"SRAW",
    	"LD",
    	"SD",
    	"MUL",
    	"MULH",
    	"MULHU",
    	"MULHSU",
    	"MULW",
    	"DIV",
    	"DIVU",
    	"REM",
    	"REMU",
    	"DIVW",
    	"DIVUW",
    	"REMW",
    	"REMUW",
    	"LRD",
    	"SCD",
    	"LRW",
    	"SCW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Rsh32x8  <t> x y) && !shiftIsBounded(v) => (SRAW <t> x                 (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [32] (ZeroExt8to64  y)))))
    (Rsh32x16 <t> x y) && !shiftIsBounded(v) => (SRAW <t> x                 (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [32] (ZeroExt16to64 y)))))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  7. test/codegen/shift.go

    	return v >> (s & 31)
    }
    
    func rshMask32x64(v int32, s uint64) int32 {
    	// arm64:"ASR",-"AND"
    	// ppc64x:"ISEL",-"ORN"
    	// riscv64:"SRAW","OR","SLTIU"
    	// s390x:-"RISBGZ",-"AND",-"LOCGR"
    	return v >> (s & 63)
    }
    
    func rsh5Mask32x64(v int32, s uint64) int32 {
    	// riscv64:"SRAW",-"OR",-"SLTIU"
    	return v >> (s & 31)
    }
    
    func lshMask64x32(v int64, s uint32) int64 {
    	// arm64:"LSL",-"AND"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/riscv/cpu.go

    	AFENCE
    	AFENCETSO
    	APAUSE
    
    	// 5.2: Integer Computational Instructions (RV64I)
    	AADDIW
    	ASLLIW
    	ASRLIW
    	ASRAIW
    	AADDW
    	ASLLW
    	ASRLW
    	ASUBW
    	ASRAW
    
    	// 5.3: Load and Store Instructions (RV64I)
    	ALD
    	ASD
    
    	// 7.1: Multiplication Operations
    	AMUL
    	AMULH
    	AMULHU
    	AMULHSU
    	AMULW
    	ADIV
    	ADIVU
    	AREM
    	AREMU
    	ADIVW
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/riscv/inst.go

    	case ASRA:
    		return &inst{0x33, 0x5, 0x0, 1024, 0x20}
    	case ASRAI:
    		return &inst{0x13, 0x5, 0x0, 1024, 0x20}
    	case ASRAIW:
    		return &inst{0x1b, 0x5, 0x0, 1024, 0x20}
    	case ASRAW:
    		return &inst{0x3b, 0x5, 0x0, 1024, 0x20}
    	case ASRET:
    		return &inst{0x73, 0x0, 0x2, 258, 0x8}
    	case ASRL:
    		return &inst{0x33, 0x5, 0x0, 0, 0x0}
    	case ASRLI:
    		return &inst{0x13, 0x5, 0x0, 0, 0x0}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.9K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "SRA", argLength: 2, reg: gp21, asm: "SRA"},                   // arg0 >> (aux1 & 63), arithmetic right shift
    		{name: "SRAW", argLength: 2, reg: gp21, asm: "SRAW"},                 // arg0 >> (aux1 & 31), arithmetic right shift of 32 bit value, sign extended to 64 bits
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
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