divwo - Code Search

src/cmd/internal/obj/ppc64/anames.go

	"BDNZ",
	"BDZ",
	"CMP",
	"CMPU",
	"CMPEQB",
	"CNTLZW",
	"CNTLZWCC",
	"CRAND",
	"CRANDN",
	"CREQV",
	"CRNAND",
	"CRNOR",
	"CROR",
	"CRORN",
	"CRXOR",
	"DIVW",
	"DIVWCC",
	"DIVWVCC",
	"DIVWV",
	"DIVWU",
	"DIVWUCC",
	"DIVWUVCC",
	"DIVWUV",
	"MODUD",
	"MODUW",
	"MODSD",
	"MODSW",
	"EQV",
	"EQVCC",
	"EXTSB",
	"EXTSBCC",
	"EXTSH",
	"EXTSHCC",
	"FABS",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Mon Apr 01 18:50:29 UTC 2024

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github.com/golang/go

src/math/big/natdiv.go

		var r2 Word
		q, r2 = z.divW(u, v[0])
		r = z2.setWord(r2)
		return
	}

	q, r = z.divLarge(z2, u, v)
	return
}

// divW returns q, r such that q = ⌊x/y⌋ and r = x%y = x - q·y.
// It uses z as the storage for q.
// Note that y is a single digit (Word), not a big number.
func (z nat) divW(x nat, y Word) (q nat, r Word) {
	m := len(x)
	switch {
	case y == 0:

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Thu Mar 14 17:02:38 UTC 2024

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github.com/golang/go

src/cmd/internal/obj/loong64/anames.go

	"CMPGEF",
	"CMPGTD",
	"CMPGTF",
	"LU12IW",
	"LU32ID",
	"LU52ID",
	"PCALAU12I",
	"PCADDU12I",
	"JIRL",
	"BGE",
	"BLT",
	"BLTU",
	"BGEU",
	"DIV",
	"DIVD",
	"DIVF",
	"DIVU",
	"DIVW",
	"LL",
	"LLV",
	"LUI",
	"MOVB",
	"MOVBU",
	"MOVD",
	"MOVDF",
	"MOVDW",
	"MOVF",
	"MOVFD",
	"MOVFW",
	"MOVH",
	"MOVHU",
	"MOVW",
	"MOVWD",
	"MOVWF",
	"MOVWL",
	"MOVWR",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed May 22 02:04:54 UTC 2024

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github.com/golang/go

src/cmd/internal/obj/riscv/anames.go

	"SLLIW",
	"SRLIW",
	"SRAIW",
	"ADDW",
	"SLLW",
	"SRLW",
	"SUBW",
	"SRAW",
	"LD",
	"SD",
	"MUL",
	"MULH",
	"MULHU",
	"MULHSU",
	"MULW",
	"DIV",
	"DIVU",
	"REM",
	"REMU",
	"DIVW",
	"DIVUW",
	"REMW",
	"REMUW",
	"LRD",
	"SCD",
	"LRW",
	"SCW",
	"AMOSWAPD",
	"AMOADDD",
	"AMOANDD",
	"AMOORD",
	"AMOXORD",
	"AMOMAXD",
	"AMOMAXUD",
	"AMOMIND",
	"AMOMINUD",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed Mar 20 14:19:33 UTC 2024

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github.com/golang/go

src/cmd/asm/internal/asm/testdata/ppc64.s

	DIVD R3, R4, R5                 // 7ca41bd2
	DIVW R3, R4                     // 7c841bd6
	DIVW R3, R4, R5                 // 7ca41bd6
	DIVDCC R3,R4, R5                // 7ca41bd3
	DIVWCC R3,R4, R5                // 7ca41bd7
	DIVDU R3, R4, R5                // 7ca41b92
	DIVWU R3, R4, R5                // 7ca41b96
	DIVDV R3, R4, R5                // 7ca41fd2
	DIVWV R3, R4, R5                // 7ca41fd6

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Fri May 17 21:53:50 UTC 2024

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github.com/golang/go

src/cmd/compile/internal/ssa/_gen/PPC64.rules

(Div64 [false] x y) => (DIVD x y)
(Div64u ...) => (DIVDU ...)
(Div32 [false] x y) => (DIVW x y)
(Div32u ...) => (DIVWU ...)
(Div16 [false]  x y) => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
(Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
(Div8 x y) => (DIVW  (SignExt8to32 x) (SignExt8to32 y))
(Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))

(Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...)

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Fri Jun 07 19:02:52 UTC 2024

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github.com/golang/go

src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

		{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"},   // arg0/arg1 (signed 64-bit)
		{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"},   // arg0/arg1 (signed 32-bit)
		{name: "DIVDU", argLength: 2, reg: gp21, asm: "DIVDU", typ: "Int64"}, // arg0/arg1 (unsigned 64-bit)
		{name: "DIVWU", argLength: 2, reg: gp21, asm: "DIVWU", typ: "Int32"}, // arg0/arg1 (unsigned 32-bit)

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed May 22 19:59:38 UTC 2024

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github.com/golang/go

src/cmd/compile/internal/ssa/_gen/RISCV64.rules

(Div(64|32)F ...) => (FDIV(D|S) ...)

(Div64 x y [false])  => (DIV x y)
(Div64u ...) => (DIVU ...)
(Div32 x y [false])  => (DIVW x y)
(Div32u ...) => (DIVUW ...)
(Div16 x y [false])  => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
(Div16u x y) => (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y))
(Div8 x y)   => (DIVW  (SignExt8to32 x)  (SignExt8to32 y))
(Div8u x y)  => (DIVUW (ZeroExt8to32 x)  (ZeroExt8to32 y))

(Hmul64 ...)  => (MULH  ...)

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Thu Mar 07 14:57:07 UTC 2024

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github.com/golang/go

src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

		{name: "DIV", argLength: 2, reg: gp21, asm: "DIV", typ: "Int64"}, // arg0 / arg1
		{name: "DIVU", argLength: 2, reg: gp21, asm: "DIVU", typ: "UInt64"},
		{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"},
		{name: "DIVUW", argLength: 2, reg: gp21, asm: "DIVUW", typ: "UInt32"},
		{name: "REM", argLength: 2, reg: gp21, asm: "REM", typ: "Int64"}, // arg0 % arg1

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Thu Mar 07 14:57:07 UTC 2024

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github.com/golang/go

src/cmd/asm/internal/asm/testdata/riscv64.s

	MULHSU	X5, X6, X7				// b3235302
	MULW	X5, X6, X7				// bb035302
	DIV	X5, X6, X7				// b3435302
	DIVU	X5, X6, X7				// b3535302
	REM	X5, X6, X7				// b3635302
	REMU	X5, X6, X7				// b3735302
	DIVW	X5, X6, X7				// bb435302
	DIVUW	X5, X6, X7				// bb535302
	REMW	X5, X6, X7				// bb635302
	REMUW	X5, X6, X7				// bb735302

	// 8.2: Load-Reserved/Store-Conditional
	LRW	(X5), X6				// 2fa30214

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Fri Mar 22 04:42:21 UTC 2024

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